+
+ wire clk;
+ wire ce;
+ wire sr;
+ wire d;
+ wire prio;
+ wire sync;
+ wire async;
+
+ assign clk = CLK_POLARITY ? CLK : ~CLK;
+ assign ce = CE_POLARITY ? CE : ~CE;
+ assign sr = SR_POLARITY ? SR : ~SR;
+ assign d = D_POLARITY ? D : ~D;
+
+ initial Q = 1'b0;
+
+ generate
+ if (SR_SYNC == 1)
+ begin
+ if (SR_SYNC_PRIORITY == 1)
+ begin
+ always @(posedge clk)
+ if (sr)
+ Q <= SR_VALUE;
+ else if (ce)
+ Q <= d;
+ end
+ else
+ begin
+ always @(posedge clk)
+ if (ce)
+ begin
+ if (sr)
+ Q <= SR_VALUE;
+ else
+ Q <= d;
+ end
+ end
+ end
+ else
+ begin
+ always @(posedge clk or posedge sr)
+ if (sr)
+ Q <= SR_VALUE;
+ else if (ce)
+ Q <= d;
+
+ end
+ endgenerate