-module GP_DCMPREF(output reg[7:0]OUT);
- parameter[7:0] REF_VAL = 8'h00;
- initial OUT = REF_VAL;
-endmodule
-
-module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
-
- always @(*) begin
- case(SEL)
- 2'd00: begin
- OUTA <= IN0;
- OUTB <= IN3;
- end
-
- 2'd01: begin
- OUTA <= IN1;
- OUTB <= IN2;
- end
-
- 2'd02: begin
- OUTA <= IN2;
- OUTB <= IN1;
- end
-
- 2'd03: begin
- OUTA <= IN3;
- OUTB <= IN0;
- end
-
- endcase
- end
-endmodule
-
-module GP_DELAY(input IN, output reg OUT);
-
- parameter DELAY_STEPS = 1;
- parameter GLITCH_FILTER = 0;
-
- initial OUT = 0;
-
- generate
-
- //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
- //Change simulation-mode delay depending on global Vdd range (how to specify this?)
- always @(*) begin
- case(DELAY_STEPS)
- 1: #166 OUT = IN;
- 2: #318 OUT = IN;
- 2: #471 OUT = IN;
- 3: #622 OUT = IN;
- default: begin
- $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
- $finish;
- end
- endcase
- end
-
- endgenerate
-
-endmodule
-
-module GP_DFF(input D, CLK, output reg Q);
- parameter [0:0] INIT = 1'bx;
- initial Q = INIT;
- always @(posedge CLK) begin
- Q <= D;
- end
-endmodule
-
-module GP_DFFI(input D, CLK, output reg nQ);
- parameter [0:0] INIT = 1'bx;
- initial nQ = INIT;
- always @(posedge CLK) begin
- nQ <= ~D;
- end
-endmodule
-
-module GP_DFFR(input D, CLK, nRST, output reg Q);
- parameter [0:0] INIT = 1'bx;
- initial Q = INIT;
- always @(posedge CLK, negedge nRST) begin
- if (!nRST)
- Q <= 1'b0;
- else
- Q <= D;
- end
-endmodule
-
-module GP_DFFRI(input D, CLK, nRST, output reg nQ);
- parameter [0:0] INIT = 1'bx;
- initial nQ = INIT;
- always @(posedge CLK, negedge nRST) begin
- if (!nRST)
- nQ <= 1'b1;
- else
- nQ <= ~D;
- end
-endmodule
-
-module GP_DFFS(input D, CLK, nSET, output reg Q);
- parameter [0:0] INIT = 1'bx;
- initial Q = INIT;
- always @(posedge CLK, negedge nSET) begin
- if (!nSET)
- Q <= 1'b1;
- else
- Q <= D;
- end
-endmodule
-
-module GP_DFFSI(input D, CLK, nSET, output reg nQ);
- parameter [0:0] INIT = 1'bx;
- initial nQ = INIT;
- always @(posedge CLK, negedge nSET) begin
- if (!nSET)
- nQ <= 1'b0;
- else
- nQ <= ~D;
- end
-endmodule
-
-module GP_DFFSR(input D, CLK, nSR, output reg Q);
- parameter [0:0] INIT = 1'bx;
- parameter [0:0] SRMODE = 1'bx;
- initial Q = INIT;
- always @(posedge CLK, negedge nSR) begin
- if (!nSR)
- Q <= SRMODE;
- else
- Q <= D;
- end
-endmodule
-
-module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
- parameter [0:0] INIT = 1'bx;
- parameter [0:0] SRMODE = 1'bx;
- initial nQ = INIT;
- always @(posedge CLK, negedge nSR) begin
- if (!nSR)
- nQ <= ~SRMODE;
- else
- nQ <= ~D;
- end
-endmodule
-
-module GP_DLATCH(input D, input nCLK, output reg Q);
- parameter [0:0] INIT = 1'bx;
- initial Q = INIT;
- always @(*) begin
- if(!nCLK)
- Q <= D;
- end
-endmodule
-
-module GP_DLATCHI(input D, input nCLK, output reg nQ);
- parameter [0:0] INIT = 1'bx;
- initial nQ = INIT;
- always @(*) begin
- if(!nCLK)
- nQ <= ~D;
- end
-endmodule
-
-module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
- parameter [0:0] INIT = 1'bx;
- initial Q = INIT;
- always @(*) begin
- if(!nRST)
- Q <= 1'b0;
- else if(!nCLK)
- Q <= D;
- end
-endmodule
-
-module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
- parameter [0:0] INIT = 1'bx;
- initial nQ = INIT;
- always @(*) begin
- if(!nRST)
- nQ <= 1'b1;
- else if(!nCLK)
- nQ <= ~D;
- end
-endmodule
-
-module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
- parameter [0:0] INIT = 1'bx;
- initial Q = INIT;
- always @(*) begin
- if(!nSET)
- Q <= 1'b1;
- else if(!nCLK)
- Q <= D;
- end
-endmodule
-
-module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
- parameter [0:0] INIT = 1'bx;
- initial nQ = INIT;
- always @(*) begin
- if(!nSET)
- nQ <= 1'b0;
- else if(!nCLK)
- nQ <= ~D;
- end
-endmodule
-
-module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
- parameter [0:0] INIT = 1'bx;
- parameter[0:0] SRMODE = 1'bx;
- initial Q = INIT;
- always @(*) begin
- if(!nSR)
- Q <= SRMODE;
- else if(!nCLK)
- Q <= D;
- end
-endmodule
-
-module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
- parameter [0:0] INIT = 1'bx;
- parameter[0:0] SRMODE = 1'bx;
- initial nQ = INIT;
- always @(*) begin
- if(!nSR)
- nQ <= ~SRMODE;
- else if(!nCLK)
- nQ <= ~D;
- end
-endmodule
-