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Merge pull request #1862 from boqwxp/cleanup_techmap
[yosys.git]
/
techlibs
/
greenpak4
/
cells_sim_digital.v
diff --git
a/techlibs/greenpak4/cells_sim_digital.v
b/techlibs/greenpak4/cells_sim_digital.v
index 043cd18d4e3dcbbd29b76cebd528c65afff8f30c..43d35d08f33c4c3c66ee49e585c756139de0bdf4 100644
(file)
--- a/
techlibs/greenpak4/cells_sim_digital.v
+++ b/
techlibs/greenpak4/cells_sim_digital.v
@@
-102,7
+102,7
@@
module GP_COUNT14(input CLK, input wire RST, output reg OUT);
default: begin
initial begin
default: begin
initial begin
- $display("Invalid RESET_MODE on GP_COUNT
8
");
+ $display("Invalid RESET_MODE on GP_COUNT
14
");
$finish;
end
end
$finish;
end
end
@@
-147,7
+147,15
@@
module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
"RISING": begin
always @(posedge CLK, posedge RST) begin
"RISING": begin
always @(posedge CLK, posedge RST) begin
- if(KEEP) begin
+ //Resets
+ if(RST) begin
+ if(RESET_VALUE == "ZERO")
+ count <= 0;
+ else
+ count <= COUNT_TO;
+ end
+
+ else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
end
else if(UP) begin
count <= count + 1'd1;
@@
-161,21
+169,21
@@
module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
count <= COUNT_TO;
end
count <= COUNT_TO;
end
+ end
+ end
+
+ "FALLING": begin
+ always @(posedge CLK, negedge RST) begin
+
//Resets
//Resets
- if(RST) begin
+ if(
!
RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
- end
- end
-
- "FALLING": begin
- always @(posedge CLK, negedge RST) begin
-
- if(KEEP) begin
+ else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
end
else if(UP) begin
count <= count + 1'd1;
@@
-189,14
+197,6
@@
module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
count <= COUNT_TO;
end
count <= COUNT_TO;
end
- //Resets
- if(!RST) begin
- if(RESET_VALUE == "ZERO")
- count <= 0;
- else
- count <= COUNT_TO;
- end
-
end
end
end
end
@@
-286,8
+286,16
@@
module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
"RISING": begin
always @(posedge CLK, posedge RST) begin
"RISING": begin
always @(posedge CLK, posedge RST) begin
+ //Resets
+ if(RST) begin
+ if(RESET_VALUE == "ZERO")
+ count <= 0;
+ else
+ count <= COUNT_TO;
+ end
+
//Main counter
//Main counter
- if(KEEP) begin
+
else
if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
end
else if(UP) begin
count <= count + 1'd1;
@@
-301,22
+309,22
@@
module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
count <= COUNT_TO;
end
count <= COUNT_TO;
end
+ end
+ end
+
+ "FALLING": begin
+ always @(posedge CLK, negedge RST) begin
+
//Resets
//Resets
- if(RST) begin
+ if(
!
RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
- end
- end
-
- "FALLING": begin
- always @(posedge CLK, negedge RST) begin
-
//Main counter
//Main counter
- if(KEEP) begin
+
else
if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
end
else if(UP) begin
count <= count + 1'd1;
@@
-330,14
+338,6
@@
module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
count <= COUNT_TO;
end
count <= COUNT_TO;
end
- //Resets
- if(!RST) begin
- if(RESET_VALUE == "ZERO")
- count <= 0;
- else
- count <= COUNT_TO;
- end
-
end
end
end
end