-cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
-
-# system simulated
-system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
-Bus())
-
-# l2cache & bus
-system.toL2Bus = Bus()
-system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
-system.l2c.num_cpus = nb_cores
-
-# connect l2c to membus
-system.l2c.mem_side = system.membus.port
-
-# add L1 caches
-for cpu in cpus:
- cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4))
- # connect cpu level-1 caches to shared level-2 cache
- cpu.connectMemPorts(system.toL2Bus)
- cpu.clock = '2GHz'
-
-# connect memory to membus
-system.physmem.port = system.membus.port
-
-
-# -----------------------
-# run simulation
-# -----------------------
-
-root = Root( system = system )
-root.system.mem_mode = 'timing'
-#root.trace.flags="Bus Cache"
-#root.trace.flags = "BusAddrRanges"
+root = BaseSESystem(mem_mode='timing', mem_class=DDR3_1600_x64,
+ cpu_class=DerivO3CPU, num_cpus=nb_cores).create_root()