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config: Add a system clock command-line option
[gem5.git]
/
tests
/
configs
/
twosys-tsunami-simple-atomic.py
diff --git
a/tests/configs/twosys-tsunami-simple-atomic.py
b/tests/configs/twosys-tsunami-simple-atomic.py
index 552acc0e1007bf13d7f7c8ec018746a57ad4ff7c..8025b4e7b0bbe881edbaa5bd74bf9e8ad2d28458 100644
(file)
--- a/
tests/configs/twosys-tsunami-simple-atomic.py
+++ b/
tests/configs/twosys-tsunami-simple-atomic.py
@@
-32,24
+32,30
@@
m5.util.addToPath('../configs/common')
from FSConfig import *
from Benchmarks import *
from FSConfig import *
from Benchmarks import *
-test_sys = makeLinuxAlphaSystem('atomic',
+test_sys = makeLinuxAlphaSystem('atomic',
SimpleMemory,
SysConfig('netperf-stream-client.rcS'))
SysConfig('netperf-stream-client.rcS'))
+test_sys.clock = '1GHz'
test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
+# create the interrupt controller
+test_sys.cpu.createInterruptController()
test_sys.cpu.connectAllPorts(test_sys.membus)
test_sys.cpu.connectAllPorts(test_sys.membus)
+test_sys.cpu.clock = '2GHz'
# In contrast to the other (one-system) Tsunami configurations we do
# not have an IO cache but instead rely on an IO bridge for accesses
# from masters on the IO bus to the memory bus
# In contrast to the other (one-system) Tsunami configurations we do
# not have an IO cache but instead rely on an IO bridge for accesses
# from masters on the IO bus to the memory bus
-test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
- ranges = [AddrRange(0, '8GB')])
+test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
-drive_sys = makeLinuxAlphaSystem('atomic',
+drive_sys = makeLinuxAlphaSystem('atomic',
SimpleMemory,
SysConfig('netperf-server.rcS'))
SysConfig('netperf-server.rcS'))
+drive_sys.clock = '1GHz'
drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
+# create the interrupt controller
+drive_sys.cpu.createInterruptController()
drive_sys.cpu.connectAllPorts(drive_sys.membus)
drive_sys.cpu.connectAllPorts(drive_sys.membus)
-drive_sys.
iobridge = Bridge(delay='50ns', nack_delay='4ns',
-
ranges = [AddrRange(0, '8GB')]
)
+drive_sys.
cpu.clock = '4GHz'
+
drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges
)
drive_sys.iobridge.slave = drive_sys.iobus.master
drive_sys.iobridge.master = drive_sys.membus.slave
drive_sys.iobridge.slave = drive_sys.iobus.master
drive_sys.iobridge.master = drive_sys.membus.slave