-system.cpu.toL2Bus.throughput 699262879 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 1907311 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 1907308 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 2330645 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 138184 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 138184 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 771752 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 771752 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 151977 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7674879 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7826856 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 438272 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311332928 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 311771200 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 311771200 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 8849920 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 4908820525 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 218162491 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3952575691 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
-system.cpu.icache.tags.replacements 5306 # number of replacements
-system.cpu.icache.tags.tagsinuse 1035.768369 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 161848074 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 6885 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 23507.345534 # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements 2545945 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4088.303608 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 421067815 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 2550041 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 165.121978 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 1812560500 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4088.303608 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.998121 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.998121 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 634 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 3418 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 851394195 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 851394195 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 272697526 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 272697526 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 148366944 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 148366944 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 421064470 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 421064470 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 421064470 # number of overall hits
+system.cpu.dcache.overall_hits::total 421064470 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 2566340 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 2566340 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 791267 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 791267 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 3357607 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3357607 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3357607 # number of overall misses
+system.cpu.dcache.overall_misses::total 3357607 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 57037182000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 57037182000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 24501570500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 24501570500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 81538752500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 81538752500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 81538752500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 81538752500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 275263866 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 275263866 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 424422077 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 424422077 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 424422077 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 424422077 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009323 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.009323 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005305 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.005305 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.007911 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.007911 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.007911 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.007911 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22225.107351 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 22225.107351 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30964.984639 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30964.984639 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24284.781542 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24284.781542 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24284.781542 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 24284.781542 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 8528 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 1295 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 875 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.746286 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 92.500000 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 2337968 # number of writebacks
+system.cpu.dcache.writebacks::total 2337968 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 800154 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 800154 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5753 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 5753 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 805907 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 805907 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 805907 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 805907 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766186 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1766186 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785514 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 785514 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2551700 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2551700 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2551700 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2551700 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33673145000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 33673145000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23618473500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 23618473500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 57291618500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 57291618500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 57291618500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 57291618500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006416 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006416 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005266 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005266 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.006012 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.006012 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19065.457998 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19065.457998 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30067.539853 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30067.539853 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements 4014 # number of replacements
+system.cpu.icache.tags.tagsinuse 1083.903563 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 216343916 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 5738 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 37703.714883 # Average number of references to valid blocks.