projects
/
gem5.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
all: Update stats for memory per master and total fix.
[gem5.git]
/
tests
/
long
/
se
/
40.perlbmk
/
ref
/
arm
/
linux
/
o3-timing
/
config.ini
diff --git
a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index 7e5e4838d44614fedae1205ecaf880e95f1083c5..d9870188cd7ee3a40bbc7267ab24c30d9c1f1652 100644
(file)
--- a/
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@
-1,6
+1,7
@@
[root]
type=Root
children=system
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@
-8,10
+9,15
@@
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
mem_mode=atomic
memories=system.physmem
num_work_ids=16
-physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@
-19,11
+25,11
@@
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.
port
[0]
+system_port=system.membus.
slave
[0]
[system.cpu]
type=DerivO3CPU
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache i
nterrupts i
tb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@
-52,6
+58,7
@@
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
@@
-69,6
+76,7
@@
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@@
-80,6
+88,7
@@
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
@@
-88,6
+97,7
@@
numRobs=1
numThreads=1
phase=0
predType=tournament
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
@@
-116,7
+126,7
@@
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
[system.cpu.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_range
s
=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
assoc=2
block_size=64
forward_snoops=true
@@
-125,30
+135,32
@@
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.
port
[1]
+mem_side=system.cpu.toL2Bus.
slave
[1]
[system.cpu.dtb]
type=ArmTLB
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
[system.cpu.fuPool]
type=FUPool
@@
-415,7
+427,7
@@
opLat=3
[system.cpu.icache]
type=BaseCache
[system.cpu.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_range
s
=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
assoc=2
block_size=64
forward_snoops=true
@@
-424,34
+436,39
@@
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
[system.cpu.l2cache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_range
s
=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
assoc=2
block_size=64
forward_snoops=true
@@
-460,36
+477,29
@@
is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.
port[2
]
-mem_side=system.membus.
port[2
]
+cpu_side=system.cpu.toL2Bus.
master[0
]
+mem_side=system.membus.
slave[1
]
[system.cpu.toL2Bus]
[system.cpu.toL2Bus]
-type=Bus
+type=
Coherent
Bus
block_size=64
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
width=64
clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.tracer]
type=ExeTracer
@@
-497,7
+507,7
@@
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM
_SE/tests/opt/long
/40.perlbmk/arm/linux/o3-timing
+cwd=build/ARM
/tests/opt/long/se
/40.perlbmk/arm/linux/o3-timing
egid=100
env=
errout=cerr
egid=100
env=
errout=cerr
@@
-514,22
+524,24
@@
system=system
uid=100
[system.membus]
uid=100
[system.membus]
-type=Bus
+type=
Coherent
Bus
block_size=64
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
width=64
clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
[system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
file=
file=
+in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.
port[1
]
+port=system.membus.
master[0
]