-system.cpu.commit.refs 908382478 # Number of memory references committed
-system.cpu.commit.loads 631387181 # Number of loads committed
-system.cpu.commit.membars 9986 # Number of memory barriers committed
-system.cpu.commit.branches 298259106 # Number of branches committed
-system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
-system.cpu.commit.function_calls 41577833 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 89265835 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3844759887 # The number of ROB reads
-system.cpu.rob.rob_writes 5783698867 # The number of ROB writes
-system.cpu.timesIdled 353367 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 42935398 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
-system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated
-system.cpu.cpi 0.925545 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.925545 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.080445 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.080445 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 11851555490 # number of integer regfile reads
-system.cpu.int_regfile_writes 2239006966 # number of integer regfile writes
-system.cpu.fp_regfile_reads 68795802 # number of floating regfile reads
-system.cpu.fp_regfile_writes 49533000 # number of floating regfile writes
-system.cpu.misc_regfile_reads 1371543913 # number of misc regfile reads
-system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 165989839 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 1492758 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 1492757 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 96304 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 4364 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 4364 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 72519 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 72519 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 52387 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3178835 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count 3231222 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1536768 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104525120 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size 106061888 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 106061888 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 279232 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 929276999 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 43029998 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2407943085 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
-system.cpu.icache.tags.replacements 22329 # number of replacements
-system.cpu.icache.tags.tagsinuse 1638.931929 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 345969528 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 24011 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 14408.792970 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1638.931929 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.800260 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.800260 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 345973619 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 345973619 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 345973619 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 345973619 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 345973619 # number of overall hits
-system.cpu.icache.overall_hits::total 345973619 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 30537 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 30537 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 30537 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 30537 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 30537 # number of overall misses
-system.cpu.icache.overall_misses::total 30537 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 527751245 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 527751245 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 527751245 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 527751245 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 527751245 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 527751245 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 346004156 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 346004156 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 346004156 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 346004156 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 346004156 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 346004156 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000088 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000088 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000088 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17282.354030 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 17282.354030 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 17282.354030 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 17282.354030 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 17282.354030 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 17282.354030 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 1734 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 32 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 54.187500 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2162 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 2162 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 2162 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 2162 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 2162 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 2162 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28375 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 28375 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 28375 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 28375 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 28375 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 28375 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 422292499 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 422292499 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 422292499 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 422292499 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 422292499 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 422292499 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000082 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14882.555031 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14882.555031 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 442208 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 32680.533022 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 1109569 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 474957 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 2.336146 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 1291.826262 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.114345 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 31338.592416 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.039423 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001529 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.956378 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.997331 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 21578 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 1057872 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1079450 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 96304 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 96304 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 6444 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 6444 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 21578 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1064316 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1085894 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 21578 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1064316 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1085894 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 2434 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 406511 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 408945 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 4361 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 4361 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 66075 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 66075 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 2434 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 472586 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 475020 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 2434 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 472586 # number of overall misses
-system.cpu.l2cache.overall_misses::total 475020 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 173732500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30711118250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 30884850750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4593677250 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 4593677250 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 173732500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 35304795500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 35478528000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 173732500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 35304795500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 35478528000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 24012 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1464383 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 1488395 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 96304 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 96304 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4364 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 4364 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 72519 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 72519 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 24012 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1536902 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1560914 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 24012 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1536902 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1560914 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101366 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277599 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.274756 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999313 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999313 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911141 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.911141 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101366 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.307493 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.304322 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101366 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.307493 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.304322 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71377.362366 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75548.062045 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 75523.238455 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69522.167991 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69522.167991 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71377.362366 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74705.546715 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74688.493116 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71377.362366 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74705.546715 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74688.493116 # average overall miss latency
+system.cpu.commit.refs 381221434 # Number of memory references committed
+system.cpu.commit.loads 252240938 # Number of loads committed
+system.cpu.commit.membars 5740 # Number of memory barriers committed
+system.cpu.commit.branches 137364860 # Number of branches committed
+system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions.
+system.cpu.commit.int_insts 682251399 # Number of committed integer instructions.
+system.cpu.commit.function_calls 19275340 # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 385756794 48.91% 48.91% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMisc 0 0.00% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 245222568 31.09% 82.76% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 125149822 15.87% 98.62% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMemRead 7018370 0.89% 99.51% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction
+system.cpu.commit.bw_lim_events 29948865 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 1524889115 # The number of ROB reads
+system.cpu.rob.rob_writes 1798376442 # The number of ROB writes
+system.cpu.timesIdled 10544 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 466491 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 640649299 # Number of Instructions Simulated
+system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 1.058298 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.058298 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.944914 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.944914 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 868460616 # number of integer regfile reads
+system.cpu.int_regfile_writes 500698081 # number of integer regfile writes
+system.cpu.fp_regfile_reads 30616065 # number of floating regfile reads
+system.cpu.fp_regfile_writes 22959495 # number of floating regfile writes
+system.cpu.cc_regfile_reads 3322380162 # number of cc regfile reads
+system.cpu.cc_regfile_writes 369206587 # number of cc regfile writes
+system.cpu.misc_regfile_reads 606831817 # number of misc regfile reads
+system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements 2756456 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.910987 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 371049565 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 2756968 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 134.586098 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 285993000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.910987 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999826 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999826 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 751745414 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 751745414 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data 243126159 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 243126159 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 127907378 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 127907378 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 371033537 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 371033537 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 371036694 # number of overall hits
+system.cpu.dcache.overall_hits::total 371036694 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 2401303 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 2401303 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1044099 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1044099 # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 3445402 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3445402 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3446049 # number of overall misses
+system.cpu.dcache.overall_misses::total 3446049 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 80431299000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 80431299000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 9946595850 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 9946595850 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 90377894850 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 90377894850 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 90377894850 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 90377894850 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 245527462 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 245527462 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 3804 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 374478939 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 374478939 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 374482743 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 374482743 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009780 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.009780 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008097 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.008097 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000348 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000348 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.009201 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.009201 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.009202 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.009202 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33494.856334 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 33494.856334 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9526.487287 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 9526.487287 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70000 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70000 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26231.451323 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26231.451323 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26226.526335 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26226.526335 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 336970 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 4742 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 71.060734 # average number of cycles each access was blocked
+system.cpu.dcache.writebacks::writebacks 2756456 # number of writebacks
+system.cpu.dcache.writebacks::total 2756456 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365826 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 365826 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323069 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 323069 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 688895 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 688895 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 688895 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 688895 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035477 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 2035477 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721030 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 721030 # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2756507 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2756507 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2757149 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2757149 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75180323500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 75180323500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5949856850 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5949856850 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5764000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5764000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 81130180350 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 81130180350 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 81135944350 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 81135944350 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36934.990422 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36934.990422 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8251.885289 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8251.885289 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8978.193146 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8978.193146 # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29432.241728 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29432.241728 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29427.479019 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 29427.479019 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements 1980154 # number of replacements
+system.cpu.icache.tags.tagsinuse 511.083769 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 245752724 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 1980664 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 124.075928 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 275035500 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 511.083769 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.998210 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.998210 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 334 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 497454087 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 497454087 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst 245752746 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 245752746 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 245752746 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 245752746 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 245752746 # number of overall hits
+system.cpu.icache.overall_hits::total 245752746 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1983875 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1983875 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1983875 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1983875 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1983875 # number of overall misses
+system.cpu.icache.overall_misses::total 1983875 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 16221042426 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 16221042426 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 16221042426 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 16221042426 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 16221042426 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 16221042426 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 247736621 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 247736621 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 247736621 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 247736621 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 247736621 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 247736621 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008008 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.008008 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.008008 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.008008 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.008008 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.008008 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8176.443791 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 8176.443791 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 8176.443791 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 8176.443791 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 8176.443791 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 8176.443791 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 85075 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 747 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 2929 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 29.045749 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 106.714286 # average number of cycles each access was blocked
+system.cpu.icache.writebacks::writebacks 1980154 # number of writebacks
+system.cpu.icache.writebacks::total 1980154 # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3028 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 3028 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 3028 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 3028 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 3028 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 3028 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980847 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 1980847 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 1980847 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 1980847 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 1980847 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 1980847 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15183658439 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 15183658439 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15183658439 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 15183658439 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15183658439 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 15183658439 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007996 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.007996 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.007996 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7665.235346 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7665.235346 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7665.235346 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 7665.235346 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7665.235346 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 7665.235346 # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.prefetcher.num_hwpf_issued 1350785 # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified 1355219 # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit 3879 # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
+system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
+system.cpu.l2cache.prefetcher.pfSpanPage 4789973 # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements 297120 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 16096.917401 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 3841839 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 313315 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 12.261906 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 15676.222250 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 420.695151 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.956801 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.025677 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.982478 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022 430 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 15765 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2 61 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3 263 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4 100 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1551 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3686 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10031 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022 0.026245 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962219 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 145605931 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 145605931 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks 735798 # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total 735798 # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks 3358223 # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total 3358223 # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 718689 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 718689 # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1976463 # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total 1976463 # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1286254 # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total 1286254 # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 1976463 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 2004943 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 3981406 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 1976463 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 2004943 # number of overall hits
+system.cpu.l2cache.overall_hits::total 3981406 # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 181 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 181 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 2160 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 2160 # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4204 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total 4204 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 749865 # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total 749865 # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 4204 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 752025 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 756229 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 4204 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 752025 # number of overall misses
+system.cpu.l2cache.overall_misses::total 756229 # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 187813000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 187813000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 349759500 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 349759500 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 63761970000 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 63761970000 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 349759500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 63949783000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 64299542500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 349759500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 63949783000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 64299542500 # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks 735798 # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total 735798 # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks 3358223 # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total 3358223 # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 181 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 181 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 720849 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 720849 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980667 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total 1980667 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036119 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total 2036119 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 1980667 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 2756968 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 4737635 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 1980667 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 2756968 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 4737635 # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002996 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.002996 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002123 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002123 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368282 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368282 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.002123 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.272772 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.159622 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.002123 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.272772 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.159622 # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86950.462963 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86950.462963 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83196.836346 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83196.836346 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85031.265628 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85031.265628 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83196.836346 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85036.778033 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 85026.549498 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83196.836346 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85036.778033 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 85026.549498 # average overall miss latency