-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 80.797237 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.019726 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits
-system.cpu.dcache.overall_hits::total 1854 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
-system.cpu.dcache.overall_misses::total 134 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 816982862 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 283 # Transaction distribution