- end if;
-
- if m_in.write_reg_enable = '1' then
- w_out.write_enable <= '1';
- w_out.write_reg <= m_in.write_reg_nr;
- w_out.write_data <= m_in.write_reg_data;
- end if;
-
- if m_in.write_cr_enable = '1' then
- c_out.write_cr_enable <= '1';
- c_out.write_cr_mask <= m_in.write_cr_mask;
- c_out.write_cr_data <= m_in.write_cr_data;
- end if;
-
- if d_in.write_reg_enable = '1' then
- w_out.write_enable <= '1';
- w_out.write_reg <= d_in.write_reg_nr;
- w_out.write_data <= d_in.write_reg_data;
- end if;
-
- if d_in.write_cr_enable = '1' then
- c_out.write_cr_enable <= '1';
- c_out.write_cr_mask <= d_in.write_cr_mask;
- c_out.write_cr_data <= d_in.write_cr_data;
+ else
+ if e_in.write_enable = '1' then
+ w_out.write_reg <= e_in.write_reg;
+ w_out.write_data <= e_in.write_data;
+ w_out.write_enable <= '1';
+ end if;
+
+ if e_in.write_cr_enable = '1' then
+ c_out.write_cr_enable <= '1';
+ c_out.write_cr_mask <= e_in.write_cr_mask;
+ c_out.write_cr_data <= e_in.write_cr_data;
+ end if;
+
+ if e_in.write_xerc_enable = '1' then
+ c_out.write_xerc_enable <= '1';
+ c_out.write_xerc_data <= e_in.xerc;
+ end if;
+
+ if fp_in.write_enable = '1' then
+ w_out.write_reg <= fp_in.write_reg;
+ w_out.write_data <= fp_in.write_data;
+ w_out.write_enable <= '1';
+ end if;
+
+ if fp_in.write_cr_enable = '1' then
+ c_out.write_cr_enable <= '1';
+ c_out.write_cr_mask <= fp_in.write_cr_mask;
+ c_out.write_cr_data <= fp_in.write_cr_data;
+ end if;
+
+ if l_in.write_enable = '1' then
+ w_out.write_reg <= l_in.write_reg;
+ w_out.write_data <= l_in.write_data;
+ w_out.write_enable <= '1';
+ end if;
+
+ if l_in.rc = '1' then
+ -- st*cx. instructions
+ scf(3) := '0';
+ scf(2) := '0';
+ scf(1) := l_in.store_done;
+ scf(0) := l_in.xerc.so;
+ c_out.write_cr_enable <= '1';
+ c_out.write_cr_mask <= num_to_fxm(0);
+ c_out.write_cr_data(31 downto 28) <= scf;
+ end if;
+
+ -- Perform CR0 update for RC forms
+ -- Note that loads never have a form with an RC bit, therefore this can test e_in.write_data
+ if e_in.rc = '1' and e_in.write_enable = '1' then
+ zero := not (or e_in.write_data(31 downto 0));
+ if e_in.mode_32bit = '0' then
+ sign := e_in.write_data(63);
+ zero := zero and not (or e_in.write_data(63 downto 32));
+ else
+ sign := e_in.write_data(31);
+ end if;
+ c_out.write_cr_enable <= '1';
+ c_out.write_cr_mask <= num_to_fxm(0);
+ cf(3) := sign;
+ cf(2) := not sign and not zero;
+ cf(1) := zero;
+ cf(0) := e_in.xerc.so;
+ c_out.write_cr_data(31 downto 28) <= cf;
+ end if;