vendor.quicklogic: enable SoC clock configuration

[nmigen.git] / .coveragerc

diff --git a/.coveragerc b/.coveragerc
index c5fad9ad461be42e88e33c32d1c8ad7248a3d537..74367c2ebbf12074bff61014ed3649fe9c793ff8 100644 (file)
--- a/.coveragerc
+++ b/.coveragerc
@@ -1,9 +1,12 @@
 [run]
 branch = True
+include =
+  nmigen/*
 omit =
   nmigen/test/*
-  */__init__.py
 
 [report]
 exclude_lines =
        :nocov:
+partial_branches =
+  :nobr: