MEM: Remove the otherPort from the cache ports

[gem5.git] / .hgignore

diff --git a/.hgignore b/.hgignore
index f536836de50bfc7f4a9fa2ef895b33b5809bc758..9e4aee18aa0f3807e919a69263eb96876c31ceca 100644 (file)
--- a/.hgignore
+++ b/.hgignore
@@ -6,3 +6,6 @@ cscope.files
 cscope.out
 *.pyc
 *~
+.*.swp
+m5out
+src/doxygen