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verilog: allow spaces in macro arguments
[yosys.git] / .travis / setup.sh
diff --git a/.travis/setup.sh b/.travis/setup.sh
index 4af0b8ee993feca32e0725f8bec5c2cb39438300..02879b974368a807e86e5b6c35e36367ea8d93cf 100755 (executable)
--- a/.travis/setup.sh
+++ b/.travis/setup.sh
@@ -51,7 +51,7 @@ fi
                git clone git://github.com/steveicarus/iverilog.git
                cd iverilog
                autoconf
-               ./configure --prefix=$HOME/.local-bin
+               CC=gcc CXX=g++ ./configure --prefix=$HOME/.local-bin
                make
                make install
                echo