add ls180.mdwn auto-generated

[libreriscv.git] / 180nm_Oct2020 / interfaces.mdwn

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 # Interfaces for the 180nm Oct2020 ASIC
 
+[[ls180]] actual interfaces
+
 [List Link](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006355.html)
 
 Bugreport and discussion at <https://bugs.libre-soc.org/show_bug.cgi?id=304>
 
 These are bare minimum viability:
+These should be easily doable with LiteX.
 
 * [[shakti/m_class/UART]]
 * [[shakti/m_class/I2C]]
@@ -21,22 +24,26 @@ Under consideration:
 
 # Secondary priorities
 
-* a PLL (this is quite a lot however it turns the ASIC from a 24mhz
-design into a 300mhz design)
-* a TLB and MMU (in combination with a PLL if it is GNU/Linux OS
-capable we have an actual viable *saleable product*, immediately)
-* dual L1 Caches with the 2x 128-bit-wide L0CacheBuffer to merge 8x LD/STs
-* multiple Common Data Buses to / from the RegFile along with a 4x
-"Striped" HI/LO-32-ODD/EVEN access pattern.
-* multi-issue
-* PartitionedSignal-based integer pipelines
-* an FP regfile and associated FP pipelines
-* SV compliance
-* 128x INT/FP registers
-* GPU-style opcodes - Jacob you mentioned Texturisation opcodes as
-being more important than e.g. SIN/COS.
-* additional interfaces such as RGB/TTL, SDRAM, HyperRAM, RGMII,
-SD/MMC, USB-ULPI
 * a pinmux
-
-TODO
+* USB - again doable with LiteX. I'm talking to Enjoy Digital about what
+  USB PHYs LiteX supports. - Yehowshua
+* SERDES for Ethernet - using LiteX and
+  [Marvell PHY](https://www.mouser.com/ProductDetail/Marvell/88E1512-A0-NNP2I000?qs=vdi0iO8H4N0XzuXqBRxTqg%3D%3D)
+* Noting that a SERDES to RGMII PHY is $20 (kinda expensive for total cost
+  of an SBC), we can instead do Eth over USB like the original RPI. This
+  moves the complexity to software - could make doing eth things during
+  boot loader a little more complex.
+
+Jacob notes:
+
+I haven't checked but I'm 99% sure that we will need to implement standard
+Power atomics, fences, ll/sc (including 128-bit version), cache flushes,
+and non-cacheable load/store operations if we want to support Linux on our
+october test chip.
+
+<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006407.html>
+
+## Alternate USB Interface Options
+ - https://github.com/im-tomu/valentyusb
+ - https://github.com/lambdaconcept/lambdaUSB
+ - https://github.com/greatscottgadgets/luna