(no commit message)

[libreriscv.git] / 180nm_Oct2020 / interfaces.mdwn

diff --git a/180nm_Oct2020/interfaces.mdwn b/180nm_Oct2020/interfaces.mdwn
index 685e3bdeb770ee55934b5e4f4348090f77ec087c..d08ff53fdbfb829f0efa7b9ba9df65d3bc58dade 100644 (file)
--- a/180nm_Oct2020/interfaces.mdwn
+++ b/180nm_Oct2020/interfaces.mdwn
@@ -1,8 +1,13 @@
 # Interfaces for the 180nm Oct2020 ASIC
 
+[[ls180]] actual interfaces
+
+[List Link](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006355.html)
+
 Bugreport and discussion at <https://bugs.libre-soc.org/show_bug.cgi?id=304>
 
 These are bare minimum viability:
+These should be easily doable with LiteX.
 
 * [[shakti/m_class/UART]]
 * [[shakti/m_class/I2C]]
@@ -19,4 +24,26 @@ Under consideration:
 
 # Secondary priorities
 
-TODO
+* a pinmux
+* USB - again doable with LiteX. I'm talking to Enjoy Digital about what
+  USB PHYs LiteX supports. - Yehowshua
+* SERDES for Ethernet - using LiteX and
+  [Marvell PHY](https://www.mouser.com/ProductDetail/Marvell/88E1512-A0-NNP2I000?qs=vdi0iO8H4N0XzuXqBRxTqg%3D%3D)
+* Noting that a SERDES to RGMII PHY is $20 (kinda expensive for total cost
+  of an SBC), we can instead do Eth over USB like the original RPI. This
+  moves the complexity to software - could make doing eth things during
+  boot loader a little more complex.
+
+Jacob notes:
+
+I haven't checked but I'm 99% sure that we will need to implement standard
+Power atomics, fences, ll/sc (including 128-bit version), cache flushes,
+and non-cacheable load/store operations if we want to support Linux on our
+october test chip.
+
+<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006407.html>
+
+## Alternate USB Interface Options
+ - https://github.com/im-tomu/valentyusb
+ - https://github.com/lambdaconcept/lambdaUSB
+ - https://github.com/greatscottgadgets/luna