| Pin | Mux0 | Mux1 | Mux2 | Mux3 |
| --- | ----------- | ----------- | ----------- | ----------- |
-| 0 | N VSS_0 | |
-| 1 | N VDD_0 | |
-| 2 | N SDR_DQM0 | |
-| 3 | N SDR_D0 | |
-| 4 | N SDR_D1 | |
-| 5 | N SDR_D2 | |
-| 6 | N SDR_D3 | |
-| 7 | N SDR_D4 | |
-| 8 | N SDR_D5 | |
-| 9 | N SDR_D6 | |
-| 10 | N SDR_D7 | |
-| 11 | N SDR_AD0 | |
-| 12 | N SDR_AD1 | |
-| 13 | N SDR_AD2 | |
-| 14 | N SDR_AD3 | |
-| 15 | N SDR_AD4 | |
-| 16 | N SDR_AD5 | |
-| 17 | N SDR_AD6 | |
-| 18 | N SDR_AD7 | |
-| 19 | N SDR_AD8 | |
-| 20 | N SDR_AD9 | |
-| 21 | N SDR_BA0 | |
-| 22 | N SDR_BA1 | |
-| 23 | N SDR_CLK | |
-| 24 | N SDR_CKE | |
-| 25 | N SDR_RASn | |
-| 26 | N SDR_CASn | |
-| 27 | N SDR_WEn | |
-| 28 | N SDR_CSn0 | |
-| 30 | N VSS_1 | |
-| 31 | N VDD_1 | |
+| 6 | N VSSE_6 | |
+| 7 | N VDDE_6 | |
+| 8 | N VDDI_6 | |
+| 9 | N VSSI_6 | |
+| 22 | N VSSI_7 | |
+| 23 | N VDDI_7 | |
+| 24 | N VSSE_7 | |
+| 25 | N VDDE_7 | |
+| 27 | N SYS_RST | |
+| 28 | N SYS_PLLCLK | |
+| 29 | N SYS_PLLSELA0 | |
+| 30 | N SYS_PLLSELA1 | |
+| 31 | N SYS_PLLTESTOUT | |
## Bank E (32 pins, width 2)
| Pin | Mux0 | Mux1 | Mux2 | Mux3 |
| --- | ----------- | ----------- | ----------- | ----------- |
-| 32 | E VSS_2 | |
-| 33 | E SDR_SDRAD10 | |
-| 34 | E SDR_SDRAD11 | |
-| 35 | E SDR_SDRAD12 | |
-| 36 | E SDR_DQM1 | |
-| 37 | E SDR_D8 | |
-| 38 | E SDR_D9 | |
-| 39 | E SDR_D10 | |
-| 40 | E SDR_D11 | |
-| 41 | E SDR_D12 | |
-| 42 | E SDR_D13 | |
-| 43 | E SDR_D14 | |
-| 44 | E SDR_D15 | |
-| 45 | E VDD_2 | |
-| 46 | E GPIOE_E8 | |
-| 47 | E GPIOE_E9 | |
-| 48 | E GPIOE_E10 | |
-| 49 | E GPIOE_E11 | |
-| 50 | E GPIOE_E12 | |
-| 51 | E GPIOE_E13 | |
-| 52 | E GPIOE_E14 | |
-| 53 | E GPIOE_E15 | |
-| 55 | E VSS_3 | |
-| 56 | E JTAG_TMS | |
-| 57 | E JTAG_TDI | |
-| 58 | E JTAG_TDO | |
-| 59 | E JTAG_TCK | |
-| 63 | E VDD_3 | |
+| 32 | E GPIOE_E0 | |
+| 33 | E GPIOE_E1 | |
+| 34 | E GPIOE_E2 | |
+| 35 | E GPIOE_E3 | |
+| 36 | E GPIOE_E4 | |
+| 37 | E GPIOE_E5 | |
+| 38 | E VSSE_4 | |
+| 39 | E VDDE_4 | |
+| 40 | E VDDI_4 | |
+| 41 | E VSSI_4 | |
+| 42 | E GPIOE_E6 | |
+| 43 | E GPIOE_E7 | |
+| 44 | E GPIOE_E8 | |
+| 45 | E JTAG_TMS | |
+| 46 | E JTAG_TDI | |
+| 47 | E JTAG_TDO | |
+| 48 | E JTAG_TCK | |
+| 49 | E GPIOE_E9 | |
+| 50 | E GPIOE_E10 | |
+| 51 | E GPIOE_E11 | |
+| 52 | E GPIOE_E12 | |
+| 53 | E GPIOE_E13 | |
+| 54 | E VSSI_5 | |
+| 55 | E VDDI_5 | |
+| 56 | E VSSE_5 | |
+| 57 | E VDDE_5 | |
+| 58 | E GPIOE_E14 | |
+| 59 | E GPIOE_E15 | |
+| 60 | E EINT_0 | |
+| 61 | E EINT_1 | |
+| 62 | E EINT_2 | |
+| 63 | E SYS_PLLVCOUT | |
## Bank S (32 pins, width 2)
| Pin | Mux0 | Mux1 | Mux2 | Mux3 |
| --- | ----------- | ----------- | ----------- | ----------- |
-| 64 | S VSS_4 | |
-| 65 | S CLK_0 | |
-| 66 | S RST_0 | |
-| 68 | S MSPI0_CK | |
-| 69 | S MSPI0_NSS | |
-| 70 | S MSPI0_MOSI | |
-| 71 | S MSPI0_MISO | |
-| 72 | S UART0_TX | |
-| 73 | S UART0_RX | |
-| 78 | S GPIOS_S0 | |
-| 79 | S GPIOS_S1 | |
-| 80 | S GPIOS_S2 | |
-| 81 | S GPIOS_S3 | |
-| 82 | S GPIOS_S4 | |
-| 83 | S GPIOS_S5 | |
-| 84 | S GPIOS_S6 | |
-| 85 | S GPIOS_S7 | |
-| 95 | S VDD_4 | |
+| 64 | S SDR_AD10 | |
+| 65 | S SDR_AD11 | |
+| 66 | S SDR_AD12 | |
+| 67 | S SDR_DQM1 | |
+| 68 | S VDDE_2 | |
+| 69 | S VSSE_2 | |
+| 70 | S VDDI_2 | |
+| 71 | S VSSI_2 | |
+| 72 | S SDR_D8 | |
+| 73 | S SDR_D9 | |
+| 74 | S SDR_D10 | |
+| 75 | S SDR_D11 | |
+| 76 | S SDR_D12 | |
+| 77 | S SDR_D13 | |
+| 78 | S SDR_D14 | |
+| 79 | S SDR_D15 | |
+| 80 | S SDR_CLK | |
+| 81 | S SDR_CKE | |
+| 82 | S SDR_RASn | |
+| 83 | S SDR_CASn | |
+| 84 | S SDR_WEn | |
+| 85 | S SDR_CSn0 | |
+| 86 | S VSSI_3 | |
+| 87 | S VDDI_3 | |
+| 88 | S VSSE_3 | |
+| 89 | S VDDE_3 | |
+| 90 | S UART0_TX | |
+| 91 | S UART0_RX | |
+| 92 | S MSPI0_CK | |
+| 93 | S MSPI0_NSS | |
+| 94 | S MSPI0_MOSI | |
+| 95 | S MSPI0_MISO | |
## Bank W (32 pins, width 2)
| Pin | Mux0 | Mux1 | Mux2 | Mux3 |
| --- | ----------- | ----------- | ----------- | ----------- |
-| 96 | W VSS_5 | |
-| 97 | W PWM_0 | |
-| 98 | W PWM_1 | |
-| 99 | W EINT_0 | |
-| 100 | W EINT_1 | |
-| 101 | W EINT_2 | |
-| 102 | W MSPI1_CK | |
-| 103 | W MSPI1_NSS | |
-| 104 | W MSPI1_MOSI | |
-| 105 | W MSPI1_MISO | |
-| 106 | W VDD_5 | |
-| 107 | W SD0_CMD | |
-| 108 | W SD0_CLK | |
-| 109 | W SD0_D0 | |
-| 110 | W SD0_D1 | |
-| 111 | W SD0_D2 | |
-| 112 | W SD0_D3 | |
-| 113 | W VSS_6 | |
-| 127 | W VDD_6 | |
+| 96 | W SDR_AD9 | |
+| 97 | W SDR_AD8 | |
+| 98 | W SDR_AD7 | |
+| 99 | W SDR_AD6 | |
+| 100 | W SDR_AD5 | |
+| 101 | W SDR_AD4 | |
+| 102 | W VDDE_0 | |
+| 103 | W VSSE_0 | |
+| 104 | W VDDI_0 | |
+| 105 | W VSSI_0 | |
+| 106 | W SDR_AD3 | |
+| 107 | W SDR_AD2 | |
+| 108 | W SDR_AD1 | |
+| 109 | W SDR_AD0 | |
+| 110 | W SDR_BA1 | |
+| 111 | W SDR_BA0 | |
+| 112 | W SDR_D7 | |
+| 113 | W SDR_D6 | |
+| 114 | W SDR_D5 | |
+| 115 | W SDR_D4 | |
+| 116 | W SDR_D3 | |
+| 117 | W SDR_D2 | |
+| 118 | W SDR_D1 | |
+| 119 | W SDR_D0 | |
+| 120 | W SDR_DQM0 | |
+| 122 | W MTWI_SDA | |
+| 123 | W MTWI_SCL | |
+| 124 | W VSSI_1 | |
+| 125 | W VDDI_1 | |
+| 126 | W VSSE_1 | |
+| 127 | W VDDE_1 | |
# Pinouts (Fixed function)
auto-generated by [[pinouts.py]]
-## CLK
-
-System Clock
-
-* CLK_0 : S1/0
-
## EINT
External Interrupt
-* EINT_0 : W3/0
-* EINT_1 : W4/0
-* EINT_2 : W5/0
+* EINT_0 : E28/0
+* EINT_1 : E29/0
+* EINT_2 : E30/0
## GPIO
GPIO
-* GPIOE_E10 : E16/0
-* GPIOE_E11 : E17/0
-* GPIOE_E12 : E18/0
-* GPIOE_E13 : E19/0
-* GPIOE_E14 : E20/0
-* GPIOE_E15 : E21/0
-* GPIOE_E8 : E14/0
-* GPIOE_E9 : E15/0
-* GPIOS_S0 : S14/0
-* GPIOS_S1 : S15/0
-* GPIOS_S2 : S16/0
-* GPIOS_S3 : S17/0
-* GPIOS_S4 : S18/0
-* GPIOS_S5 : S19/0
-* GPIOS_S6 : S20/0
-* GPIOS_S7 : S21/0
+* GPIOE_E0 : E0/0
+* GPIOE_E1 : E1/0
+* GPIOE_E10 : E18/0
+* GPIOE_E11 : E19/0
+* GPIOE_E12 : E20/0
+* GPIOE_E13 : E21/0
+* GPIOE_E14 : E26/0
+* GPIOE_E15 : E27/0
+* GPIOE_E2 : E2/0
+* GPIOE_E3 : E3/0
+* GPIOE_E4 : E4/0
+* GPIOE_E5 : E5/0
+* GPIOE_E6 : E10/0
+* GPIOE_E7 : E11/0
+* GPIOE_E8 : E12/0
+* GPIOE_E9 : E17/0
## JTAG
JTAG
-* JTAG_TCK : E27/0
-* JTAG_TDI : E25/0
-* JTAG_TDO : E26/0
-* JTAG_TMS : E24/0
+* JTAG_TCK : E16/0
+* JTAG_TDI : E14/0
+* JTAG_TDO : E15/0
+* JTAG_TMS : E13/0
## MSPI0
-SPI (Serial Peripheral Interface) Master 1
-
-* MSPI0_CK : S4/0
-* MSPI0_MISO : S7/0
-* MSPI0_MOSI : S6/0
-* MSPI0_NSS : S5/0
-
-## MSPI1
-
-SPI (Serial Peripheral Interface) Master 2
-
-* MSPI1_CK : W6/0
-* MSPI1_MISO : W9/0
-* MSPI1_MOSI : W8/0
-* MSPI1_NSS : W7/0
-
-## PWM
-
-PWM
-
-* PWM_0 : W1/0
-* PWM_1 : W2/0
-
-## RST
+SPI Master 1 (general)
-Reset
+* MSPI0_CK : S28/0
+* MSPI0_MISO : S31/0
+* MSPI0_MOSI : S30/0
+* MSPI0_NSS : S29/0
-* RST_0 : S2/0
+## MTWI
-## SD0
+I2C Master 1
-SD/MMC 1
-
-* SD0_CLK : W12/0
-* SD0_CMD : W11/0
-* SD0_D0 : W13/0
-* SD0_D1 : W14/0
-* SD0_D2 : W15/0
-* SD0_D3 : W16/0
+* MTWI_SCL : W27/0
+* MTWI_SDA : W26/0
## SDR
SDRAM
-* SDR_AD0 : N11/0
-* SDR_AD1 : N12/0
-* SDR_AD2 : N13/0
-* SDR_AD3 : N14/0
-* SDR_AD4 : N15/0
-* SDR_AD5 : N16/0
-* SDR_AD6 : N17/0
-* SDR_AD7 : N18/0
-* SDR_AD8 : N19/0
-* SDR_AD9 : N20/0
-* SDR_BA0 : N21/0
-* SDR_BA1 : N22/0
-* SDR_CASn : N26/0
-* SDR_CKE : N24/0
-* SDR_CLK : N23/0
-* SDR_CSn0 : N28/0
-* SDR_D0 : N3/0
-* SDR_D1 : N4/0
-* SDR_D10 : E7/0
-* SDR_D11 : E8/0
-* SDR_D12 : E9/0
-* SDR_D13 : E10/0
-* SDR_D14 : E11/0
-* SDR_D15 : E12/0
-* SDR_D2 : N5/0
-* SDR_D3 : N6/0
-* SDR_D4 : N7/0
-* SDR_D5 : N8/0
-* SDR_D6 : N9/0
-* SDR_D7 : N10/0
-* SDR_D8 : E5/0
-* SDR_D9 : E6/0
-* SDR_DQM0 : N2/0
-* SDR_DQM1 : E4/0
-* SDR_RASn : N25/0
-* SDR_SDRAD10 : E1/0
-* SDR_SDRAD11 : E2/0
-* SDR_SDRAD12 : E3/0
-* SDR_WEn : N27/0
+* SDR_AD0 : W13/0
+* SDR_AD1 : W12/0
+* SDR_AD10 : S0/0
+* SDR_AD11 : S1/0
+* SDR_AD12 : S2/0
+* SDR_AD2 : W11/0
+* SDR_AD3 : W10/0
+* SDR_AD4 : W5/0
+* SDR_AD5 : W4/0
+* SDR_AD6 : W3/0
+* SDR_AD7 : W2/0
+* SDR_AD8 : W1/0
+* SDR_AD9 : W0/0
+* SDR_BA0 : W15/0
+* SDR_BA1 : W14/0
+* SDR_CASn : S19/0
+* SDR_CKE : S17/0
+* SDR_CLK : S16/0
+* SDR_CSn0 : S21/0
+* SDR_D0 : W23/0
+* SDR_D1 : W22/0
+* SDR_D10 : S10/0
+* SDR_D11 : S11/0
+* SDR_D12 : S12/0
+* SDR_D13 : S13/0
+* SDR_D14 : S14/0
+* SDR_D15 : S15/0
+* SDR_D2 : W21/0
+* SDR_D3 : W20/0
+* SDR_D4 : W19/0
+* SDR_D5 : W18/0
+* SDR_D6 : W17/0
+* SDR_D7 : W16/0
+* SDR_D8 : S8/0
+* SDR_D9 : S9/0
+* SDR_DQM0 : W24/0
+* SDR_DQM1 : S3/0
+* SDR_RASn : S18/0
+* SDR_WEn : S20/0
+
+## SYS
+
+System Control
+
+* SYS_PLLCLK : N28/0
+* SYS_PLLSELA0 : N29/0
+* SYS_PLLSELA1 : N30/0
+* SYS_PLLTESTOUT : N31/0
+* SYS_PLLVCOUT : E31/0
+* SYS_RST : N27/0
## UART0
UART (TX/RX) 1
-* UART0_RX : S9/0
-* UART0_TX : S8/0
+* UART0_RX : S27/0
+* UART0_TX : S26/0
## VDD
Power
-* VDD_0 : N1/0
-* VDD_1 : N31/0
-* VDD_2 : E13/0
-* VDD_3 : E31/0
-* VDD_4 : S31/0
-* VDD_5 : W10/0
-* VDD_6 : W31/0
+* VDDE_0 : W6/0
+* VDDE_1 : W31/0
+* VDDE_2 : S4/0
+* VDDE_3 : S25/0
+* VDDE_4 : E7/0
+* VDDE_5 : E25/0
+* VDDE_6 : N7/0
+* VDDE_7 : N25/0
+* VDDI_0 : W8/0
+* VDDI_1 : W29/0
+* VDDI_2 : S6/0
+* VDDI_3 : S23/0
+* VDDI_4 : E8/0
+* VDDI_5 : E23/0
+* VDDI_6 : N8/0
+* VDDI_7 : N23/0
## VSS
GND
-* VSS_0 : N0/0
-* VSS_1 : N30/0
-* VSS_2 : E0/0
-* VSS_3 : E23/0
-* VSS_4 : S0/0
-* VSS_5 : W0/0
-* VSS_6 : W17/0
+* VSSE_0 : W7/0
+* VSSE_1 : W30/0
+* VSSE_2 : S5/0
+* VSSE_3 : S24/0
+* VSSE_4 : E6/0
+* VSSE_5 : E24/0
+* VSSE_6 : N6/0
+* VSSE_7 : N24/0
+* VSSI_0 : W9/0
+* VSSI_1 : W28/0
+* VSSI_2 : S7/0
+* VSSI_3 : S22/0
+* VSSI_4 : E9/0
+* VSSI_5 : E22/0
+* VSSI_6 : N9/0
+* VSSI_7 : N22/0
# Pinmap for Libre-SOC 180nm
-## SD0
-
-user-facing: internal (on Card), multiplexed with JTAG
-and UART2, for debug purposes
-
-* SD0_CMD 107 W11/0
-* SD0_CLK 108 W12/0
-* SD0_D0 109 W13/0
-* SD0_D1 110 W14/0
-* SD0_D2 111 W15/0
-* SD0_D3 112 W16/0
-
## UART0
-* UART0_TX 72 S8/0
-* UART0_RX 73 S9/0
+* UART0_TX 90 S26/0
+* UART0_RX 91 S27/0
## GPIOS
-* GPIOS_S0 78 S14/0
-* GPIOS_S1 79 S15/0
-* GPIOS_S2 80 S16/0
-* GPIOS_S3 81 S17/0
-* GPIOS_S4 82 S18/0
-* GPIOS_S5 83 S19/0
-* GPIOS_S6 84 S20/0
-* GPIOS_S7 85 S21/0
## GPIOE
-* GPIOE_E8 46 E14/0
-* GPIOE_E9 47 E15/0
-* GPIOE_E10 48 E16/0
-* GPIOE_E11 49 E17/0
-* GPIOE_E12 50 E18/0
-* GPIOE_E13 51 E19/0
-* GPIOE_E14 52 E20/0
-* GPIOE_E15 53 E21/0
+* GPIOE_E0 32 E0/0
+* GPIOE_E1 33 E1/0
+* GPIOE_E2 34 E2/0
+* GPIOE_E3 35 E3/0
+* GPIOE_E4 36 E4/0
+* GPIOE_E5 37 E5/0
+* GPIOE_E6 42 E10/0
+* GPIOE_E7 43 E11/0
+* GPIOE_E8 44 E12/0
+* GPIOE_E9 49 E17/0
+* GPIOE_E10 50 E18/0
+* GPIOE_E11 51 E19/0
+* GPIOE_E12 52 E20/0
+* GPIOE_E13 53 E21/0
+* GPIOE_E14 58 E26/0
+* GPIOE_E15 59 E27/0
## JTAG
-* JTAG_TMS 56 E24/0
-* JTAG_TDI 57 E25/0
-* JTAG_TDO 58 E26/0
-* JTAG_TCK 59 E27/0
+* JTAG_TMS 45 E13/0
+* JTAG_TDI 46 E14/0
+* JTAG_TDO 47 E15/0
+* JTAG_TCK 48 E16/0
## PWM
-* PWM_0 97 W1/0
-* PWM_1 98 W2/0
## EINT
-* EINT_0 99 W3/0
-* EINT_1 100 W4/0
-* EINT_2 101 W5/0
+* EINT_0 60 E28/0
+* EINT_1 61 E29/0
+* EINT_2 62 E30/0
## VDD
-* VDD_0 1 N1/0
-* VDD_1 31 N31/0
-* VDD_2 45 E13/0
-* VDD_3 63 E31/0
-* VDD_4 95 S31/0
-* VDD_5 106 W10/0
-* VDD_6 127 W31/0
+* VDDE_6 7 N7/0
+* VDDI_6 8 N8/0
+* VDDI_7 23 N23/0
+* VDDE_7 25 N25/0
+* VDDE_4 39 E7/0
+* VDDI_4 40 E8/0
+* VDDI_5 55 E23/0
+* VDDE_5 57 E25/0
## VSS
-* VSS_0 0 N0/0
-* VSS_1 30 N30/0
-* VSS_2 32 E0/0
-* VSS_3 55 E23/0
-* VSS_4 64 S0/0
-* VSS_5 96 W0/0
-* VSS_6 113 W17/0
-
-## CLK
-
+* VSSE_6 6 N6/0
+* VSSI_6 9 N9/0
+* VSSI_7 22 N22/0
+* VSSE_7 24 N24/0
+* VSSE_4 38 E6/0
+* VSSI_4 41 E9/0
+* VSSI_5 54 E22/0
+* VSSE_5 56 E24/0
+## SYS
-* CLK_0 65 S1/0
-## RST
+* SYS_RST 27 N27/0
+* SYS_PLLCLK 28 N28/0
+* SYS_PLLSELA0 29 N29/0
+* SYS_PLLSELA1 30 N30/0
+* SYS_PLLTESTOUT 31 N31/0
+* SYS_PLLVCOUT 63 E31/0
+## MTWI
-* RST_0 66 S2/0
+I2C.
-## TWI0
+* MTWI_SDA 122 W26/0
+* MTWI_SCL 123 W27/0
## MSPI0
-* MSPI0_CK 68 S4/0
-* MSPI0_NSS 69 S5/0
-* MSPI0_MOSI 70 S6/0
-* MSPI0_MISO 71 S7/0
-
-## MSPI1
-
-
-
-* MSPI1_CK 102 W6/0
-* MSPI1_NSS 103 W7/0
-* MSPI1_MOSI 104 W8/0
-* MSPI1_MISO 105 W9/0
+* MSPI0_CK 92 S28/0
+* MSPI0_NSS 93 S29/0
+* MSPI0_MOSI 94 S30/0
+* MSPI0_MISO 95 S31/0
## SDR
-* SDR_DQM0 2 N2/0
-* SDR_D0 3 N3/0
-* SDR_D1 4 N4/0
-* SDR_D2 5 N5/0
-* SDR_D3 6 N6/0
-* SDR_D4 7 N7/0
-* SDR_D5 8 N8/0
-* SDR_D6 9 N9/0
-* SDR_D7 10 N10/0
-* SDR_AD0 11 N11/0
-* SDR_AD1 12 N12/0
-* SDR_AD2 13 N13/0
-* SDR_AD3 14 N14/0
-* SDR_AD4 15 N15/0
-* SDR_AD5 16 N16/0
-* SDR_AD6 17 N17/0
-* SDR_AD7 18 N18/0
-* SDR_AD8 19 N19/0
-* SDR_AD9 20 N20/0
-* SDR_BA0 21 N21/0
-* SDR_BA1 22 N22/0
-* SDR_CLK 23 N23/0
-* SDR_CKE 24 N24/0
-* SDR_RASn 25 N25/0
-* SDR_CASn 26 N26/0
-* SDR_WEn 27 N27/0
-* SDR_CSn0 28 N28/0
-* SDR_SDRAD10 33 E1/0
-* SDR_SDRAD11 34 E2/0
-* SDR_SDRAD12 35 E3/0
-* SDR_DQM1 36 E4/0
-* SDR_D8 37 E5/0
-* SDR_D9 38 E6/0
-* SDR_D10 39 E7/0
-* SDR_D11 40 E8/0
-* SDR_D12 41 E9/0
-* SDR_D13 42 E10/0
-* SDR_D14 43 E11/0
-* SDR_D15 44 E12/0
+* SDR_AD10 64 S0/0
+* SDR_AD11 65 S1/0
+* SDR_AD12 66 S2/0
+* SDR_DQM1 67 S3/0
+* SDR_D8 72 S8/0
+* SDR_D9 73 S9/0
+* SDR_D10 74 S10/0
+* SDR_D11 75 S11/0
+* SDR_D12 76 S12/0
+* SDR_D13 77 S13/0
+* SDR_D14 78 S14/0
+* SDR_D15 79 S15/0
+* SDR_CLK 80 S16/0
+* SDR_CKE 81 S17/0
+* SDR_RASn 82 S18/0
+* SDR_CASn 83 S19/0
+* SDR_WEn 84 S20/0
+* SDR_CSn0 85 S21/0
+* SDR_AD9 96 W0/0
+* SDR_AD8 97 W1/0
+* SDR_AD7 98 W2/0
+* SDR_AD6 99 W3/0
+* SDR_AD5 100 W4/0
+* SDR_AD4 101 W5/0
+* SDR_AD3 106 W10/0
+* SDR_AD2 107 W11/0
+* SDR_AD1 108 W12/0
+* SDR_AD0 109 W13/0
+* SDR_BA1 110 W14/0
+* SDR_BA0 111 W15/0
+* SDR_D7 112 W16/0
+* SDR_D6 113 W17/0
+* SDR_D5 114 W18/0
+* SDR_D4 115 W19/0
+* SDR_D3 116 W20/0
+* SDR_D2 117 W21/0
+* SDR_D1 118 W22/0
+* SDR_D0 119 W23/0
+* SDR_DQM0 120 W24/0
## Unused Pinouts (spare as GPIO) for 'Libre-SOC 180nm'
| Pin | Mux0 | Mux1 | Mux2 | Mux3 |
| --- | ----------- | ----------- | ----------- | ----------- |
+| 68 | S VDDE_2 | | | |
+| 69 | S VSSE_2 | | | |
+| 70 | S VDDI_2 | | | |
+| 71 | S VSSI_2 | | | |
+| 86 | S VSSI_3 | | | |
+| 87 | S VDDI_3 | | | |
+| 88 | S VSSE_3 | | | |
+| 89 | S VDDE_3 | | | |
+| 102 | W VDDE_0 | | | |
+| 103 | W VSSE_0 | | | |
+| 104 | W VDDI_0 | | | |
+| 105 | W VSSI_0 | | | |
+| 124 | W VSSI_1 | | | |
+| 125 | W VDDI_1 | | | |
+| 126 | W VSSE_1 | | | |
+| 127 | W VDDE_1 | | | |
# Reference Datasheets
datasheets and pinout links
+
* <http://datasheets.chipdb.org/AMD/8018x/80186/amd-80186.pdf>
* <http://hands.com/~lkcl/eoma/shenzen/frida/FRD144A2701.pdf>
* <http://pinouts.ru/Memory/sdcard_pinout.shtml>