This page is for discussion of what we can aim for and reasonably achieve.
To be expanded with links to bugreports
+Links:
+
+* <https://gitlab.com/Chips4Makers>
+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/007699.html>
+
## Minimum viability
* a Wishbone interface. this allows us to drop *directly* into
* additional interfaces such as RGB/TTL, SDRAM, HyperRAM, RGMII, SD/MMC,
USB-ULPI
* a pinmux
+* [FSI instead of JTAG](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga/-/blob/master/fsi_master.v)
# Available people
* [[programmerjake]] TODO
* [[Yehowshua_Immanuel]] - Delegate interfaces and do timeline/cost projections
* [[mnolan]] pipelines
-* [[tplaten]] TODO
+* [[tplaten]] memory and cache
* [[jock_tanner]] TODO
* MarketNext TODO
+# Preliminary coriolis2 ASIC layout
+
+## 02jul2020 - first version
+
+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-July/008438.html>
+
+[[!img 180nm_Oct2020/2020-07-02_19-01.png size="900x" ]]
+
+## 03jul2020 - DIV unit added
+
+[[!img 180nm_Oct2020/2020-07-03_11-04.png size="900x" ]]
+