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[libreriscv.git] / 180nm_Oct2020.mdwn

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@@ -3,6 +3,11 @@
 This page is for discussion of what we can aim for and reasonably achieve.
 To be expanded with links to bugreports
 
+Links:
+
+* <https://gitlab.com/Chips4Makers>
+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/007699.html>
+
 ## Minimum viability
 
 * a Wishbone interface.  this allows us to drop *directly* into
@@ -14,14 +19,15 @@ To be expanded with links to bugreports
 * so are multiple register file files (SPRs, Condition Regs, 32x INT Regs)
 * the integer pipelines (integer and logic instructions) are essential
   (the FP ones not so much)
+  <https://bugs.libre-soc.org/show_bug.cgi?id=305>
 * a very very basic Branch Prediction system (fixed, but observing POWER
   branch "hints")
 * a very very basic Common Data Bus infrastructure.
 * a TLB and MMU are not strictly essential (not for a proof-of-concept ASIC)
 * neither in some ways is a L1 cache
-* [[180nm_Oct2020/interfaces]] we need as a bare minimum include GPIO, EINT, SPI and QSPI,
-  I2C, UART16550, LPC (from Raptor Engineering) and that actually might
-  even be it.
+* [[180nm_Oct2020/interfaces]] we need as a bare minimum include JTAG,
+  GPIO, EINT, SPI and QSPI, I2C, UART16550, LPC (from Raptor Engineering)
+  and that actually might even be it.
 
 ## Secondary priorities
 
@@ -42,15 +48,28 @@ To be expanded with links to bugreports
 * additional interfaces such as RGB/TTL, SDRAM, HyperRAM, RGMII, SD/MMC,
   USB-ULPI
 * a pinmux
+* [FSI instead of JTAG](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga/-/blob/master/fsi_master.v)
 
 # Available people
 
 * Rudi from <http://asics.ws> to cover the interface set
 * [[lkcl]] for the scoreboard systems
 * [[programmerjake]] TODO
-* [[Yehowshua_Immanuel]] TODO
-* [[mtnolan]] TODO
-* [[tplaten]] TODO
+* [[Yehowshua_Immanuel]] - Delegate interfaces and do timeline/cost projections
+* [[mnolan]] pipelines 
+* [[tplaten]] memory and cache
 * [[jock_tanner]] TODO
 * MarketNext TODO
 
+# Preliminary coriolis2 ASIC layout
+
+## 02jul2020 - first version
+
+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-July/008438.html>
+
+[[!img 180nm_Oct2020/2020-07-02_19-01.png size="900x" ]]
+
+## 03jul2020 - DIV unit added
+
+[[!img 180nm_Oct2020/2020-07-03_11-04.png size="900x" ]]
+