# 180 nm ASIC plan for Oct 2020
+NOTE: moved to Jun 9th 2021 (sigh should not have put a date in the page name, oh well)
+
This page is for discussion of what we can aim for and reasonably achieve.
To be expanded with links to bugreports
* [[180nm_Oct2020/interfaces]] we need as a bare minimum include JTAG,
GPIO, EINT, SPI and QSPI, I2C, UART16550, LPC (from Raptor Engineering)
and that actually might even be it.
+* [[180nm_Oct2020/ls180]] actual auto-generated pinouts by pinmux program
## Secondary priorities
* [[programmerjake]] TODO
* [[Yehowshua_Immanuel]] - Delegate interfaces and do timeline/cost projections
* [[mnolan]] pipelines
-* [[tplaten]] TODO
+* [[tplaten]] memory and cache
* [[jock_tanner]] TODO
* MarketNext TODO
[[!img 180nm_Oct2020/2020-07-03_11-04.png size="900x" ]]
+## 28dec2020 - End of year progress update
+
+### With blockage layers
+
+[[!img 180nm_Oct2020/2020-12-28.png size="900x" ]]
+
+### Without blockage layers so wires can be seen more clearly
+
+[[!img 180nm_Oct2020/2020-12-28_without_blockages.png size="900x" ]]