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[libreriscv.git] / 180nm_Oct2020.mdwn
index 89002eec75fd4111778c8ef21557aab7b35df8f8..cbd96a61abd09add294cf77410c499875e83e9df 100644 (file)
@@ -3,6 +3,11 @@
 This page is for discussion of what we can aim for and reasonably achieve.
 To be expanded with links to bugreports
 
+Links:
+
+* <https://gitlab.com/Chips4Makers>
+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/007699.html>
+
 ## Minimum viability
 
 * a Wishbone interface.  this allows us to drop *directly* into
@@ -43,14 +48,15 @@ To be expanded with links to bugreports
 * additional interfaces such as RGB/TTL, SDRAM, HyperRAM, RGMII, SD/MMC,
   USB-ULPI
 * a pinmux
+* [FSI instead of JTAG](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga/-/blob/master/fsi_master.v)
 
 # Available people
 
 * Rudi from <http://asics.ws> to cover the interface set
 * [[lkcl]] for the scoreboard systems
 * [[programmerjake]] TODO
-* [[Yehowshua_Immanuel]] TODO
-* [[mtnolan]] pipelines 
+* [[Yehowshua_Immanuel]] - Delegate interfaces and do timeline/cost projections
+* [[mnolan]] pipelines 
 * [[tplaten]] TODO
 * [[jock_tanner]] TODO
 * MarketNext TODO