(no commit message)

[libreriscv.git] / 3d_gpu / architecture / regfile.mdwn

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
index 551d54a16d7ca0f9b52fe5df8ebb74c80c5e0a43..483ea4b496b089e709e67064678a83655706887e 100644 (file)
--- a/3d_gpu/architecture/regfile.mdwn
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -1,11 +1,17 @@
 # Register Files
 
-A minimum of 3 register files are required for POWER:
+Discussion:
+
+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008368.html>
+
+These register files are required for POWER:
 
 * Floating-point
 * Integer
-* Control and Condition Code Registers (CR0-7, CTR, LR)
+* Control and Condition Code Registers (CR0-7)
 * SPRs (Special Purpose Registers)
+* Fast Registers (CTR, LR, SRR0, SRR1 etc.)
+* "State" Registers (CIA, MSR, SimpleV VL)
 
 Source code:
 
@@ -23,14 +29,16 @@ For a GPU, the FP and Integer registers need to be a massive 128 x 64-bit.
   - CA(32) - 2-bit
   - OV(32) - 2-bit
   - SO     - 1 bit
-* FAST regfile: 7x 64-bit, full 3R2W (possibly greater)
-  - MSR: 64-bit
-  - PC: 64-bit
+* FAST regfile: 5x 64-bit, full 3R2W (possibly greater)
   - LR: 64-bit
   - CTR: 64-bit
   - TAR: 64-bit
   - SRR1: 64-bit
   - SRR2: 64-bit
+* STATE regfile: 3x 64-bit, 2R1W (possibly greater)
+  - MSR: 64-bit
+  - PC: 64-bit
+  - SVSTATE: 64-bit
 
 # Connectivity between regfiles and Function Units