# Register Files
-A minimum of 3 register files are required for POWER:
+Discussion:
+
+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008368.html>
+
+These register files are required for POWER:
* Floating-point
* Integer
-* Control and Condition Code Registers (CR0-7, CTR, LR)
+* Control and Condition Code Registers (CR0-7)
* SPRs (Special Purpose Registers)
+* Fast Registers (CTR, LR, SRR0, SRR1 etc.)
+* "State" Registers (CIA, MSR, SimpleV VL)
+
+Source code:
+
+* <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/regfiles.py;hb=HEAD>
+
+For a GPU, the FP and Integer registers need to be a massive 128 x 64-bit.
+
+# Regfile groups, Port Allocations and bit-widths
-The FP and Integer registers need to be a massive 128 x 64-bit.
+* INT regfile: 32x 64-bit with 4R1W
+* SPR regfile: 1024x 64-bit (!) needs a "map" on that 1R1W
+* CR regfile: 8x 4-bit with full 8R8W (for full 32-bit read/write)
+ - CR0-7: 4-bit
+* XER regfile: 2x 2-bit, 1x 1-bit with full 3R3W
+ - CA(32) - 2-bit
+ - OV(32) - 2-bit
+ - SO - 1 bit
+* FAST regfile: 5x 64-bit, full 3R2W (possibly greater)
+ - LR: 64-bit
+ - CTR: 64-bit
+ - TAR: 64-bit
+ - SRR1: 64-bit
+ - SRR2: 64-bit
+* STATE regfile: 3x 64-bit, 2R1W (possibly greater)
+ - MSR: 64-bit
+ - PC: 64-bit
+ - SVSTATE: 64-bit
# Connectivity between regfiles and Function Units
Click on the image to expand it full-screen:
[[!img regfile_hilo_32_odd_even.png size="500px"]]
+
+# Regspecs
+
+* Source: <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/regspec.py;hb=HEAD>
+
+"Regspecs" is a term used for describing the relationship between register files,
+register file ports, register widths, and the Computation Units that they connect
+to.
+
+Regspecs are defined, in python, as follows:
+
+| Regfile name | CompUnit Record name | bit range register mapping |
+| ---- | ---------- | ------------ |
+| INT | ra | 0:3,5 |
+
+Description of each heading:
+
+* Regfile name: INT corresponds to the INTEGER file, CR to Condition Register etc.
+* CompUnit Record name: in the Input or Output Record there will be a signal by
+ name. This field refers to that record signal, thus providing a sequential
+ ordering for the fields.
+* Bit range: this is specified as an *inclusive* range of the form "start:end"
+ or just a single bit, "N". Multiple ranges may be specified, and are
+ comma-separated.
+
+Here is how they are used:
+```
+class CRInputData(IntegerData):
+ regspec = [('INT', 'a', '0:63'), # 64 bit range
+ ('INT', 'b', '0:63'), # 6B bit range
+ ('CR', 'full_cr', '0:31'), # 32 bit range
+ ('CR', 'cr_a', '0:3'), # 4 bit range
+ ('CR', 'cr_b', '0:3'), # 4 bit range
+ ('CR', 'cr_c', '0:3')] # 4 bit range
+```
+
+This tells us, when used by MultiCompUnit, that:
+
+* CompUnit src reg 0 is from the INT regfile, is linked to CRInputData.a, 64-bit
+* CompUnit src reg 1 is from the INT regfile, is linked to CRInputData.b, 64-bit
+* CompUnit src reg 2 is from the CR regfile, is CRInputData.full\_cr, and 32-bit
+* CompUnit src reg 3 is from the CR regfile, is CRInputData.cr\_a, and 4-bit
+* CompUnit src reg 4 is from the CR regfile, is CRInputData.cr\_b, and 4-bit
+* CompUnit src reg 5 is from the CR regfile, is CRInputData.cr\_c, and 4-bit
+
+Likewise there is a corresponding regspec for CROutputData. The two are combined
+and associated with the Pipeline:
+
+```
+class CRPipeSpec(CommonPipeSpec):
+ regspec = (CRInputData.regspec, CROutputData.regspec)
+ opsubsetkls = CompCROpSubset
+```
+
+In this way the pipeline can be connected up to a generic, general-purpose class
+(MultiCompUnit), which would otherwise know nothing about the details of the ALU
+(Pipeline) that it is being connected to.
+
+In addition, on the other side of the MultiCompUnit, the regspecs contain enough
+information to be able to wire up batches of MultiCompUnits (now known, because
+of their association with an ALU, as FunctionUnits), associating the MultiCompUnits
+correctly with their corresponding Register File.
+
+Note: there are two exceptions to the "generic-ness and abstraction"
+where MultiCompUnit "knows nothing":
+
+1. When the Operand Subset has a member "zero_a". this tells MultiCompUnit
+ to create a multiplexer that, if operand.zero_a is set, will put **ZERO**
+ into its first src operand (src_i[0]) and it will **NOT** put out a
+ read request (**NOT** raise rd.req[0]) for that first register.
+2. When the Operand Subset has a member "imm_data". this tells
+ MultiCompUnit to create a multiplexer that, if operand.imm_data.ok is
+ set, will copy operand.imm_data into its *second* src operand (src_i[1]).
+ Further: that it will **NOT** put out a read request (**NOT** raise
+ rd.req[1]) for that second register.
+
+These should only be activated for INTEGER and Logical pipelines, and
+the regspecs for them must note and respect the requirements: input
+regspec[0] may *only* be associated with operand.zero_a, and input
+regspec[1] may *only* be associated with operand.imm_data. the POWER9
+Decoder and the actual INTEGER and Logical pipelines have these
+expectations **specifically** hard-coded into them.
projects / libreriscv.git / blobdiff