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[libreriscv.git] / 3d_gpu / architecture / regfile.mdwn

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
index 8f5f04d6949a5ebba62dac78c82aa1e9591d06ae..86e69944b02c0aba83244aef344bee6d5b8de34f 100644 (file)
--- a/3d_gpu/architecture/regfile.mdwn
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -83,6 +83,8 @@ Regspecs are defined, in python, as follows:
 | ----         | ----------           | ------------               |
 | INT          | ra                   | 0:3,5                      |
 
+Description of each heading:
+
 * Regfile name: INT corresponds to the INTEGER file, CR to Condition Register etc.
 * CompUnit Record name: in the Input or Output Record there will be a signal by
   name.  This field refers to that record signal, thus providing a sequential