add WIP bigint-mul-pipe.dia

[libreriscv.git] / 3d_gpu / layouts / coriolis2_180nm.mdwn

diff --git a/3d_gpu/layouts/coriolis2_180nm.mdwn b/3d_gpu/layouts/coriolis2_180nm.mdwn
index b76b31e746c40245334fab5bf360d6a4e716aa1b..c6f67ec9af54b7ce3679a69076db54ca79f5850a 100644 (file)
--- a/3d_gpu/layouts/coriolis2_180nm.mdwn
+++ b/3d_gpu/layouts/coriolis2_180nm.mdwn
@@ -6,8 +6,6 @@
 * <https://ftp.libre-soc.org/course_18oct2021>
 * [[180nm_Oct2020]]
 
-<img src="https://ftp.libre-soc.org/course_18oct2021/drawing-2.svg" width=500 />
-
 # Simple floorplan
 
 [[!img simple_floorplan.png size="500x"]]
@@ -56,6 +54,8 @@ with a proper connection to the Memory Bus (wishbone).
 
 # IO Ring and JTAG
 
+[[!img 180nm_Oct2020/ls180.svg size="500x" ]]
+
 The IO Ring is autogenerated from the same pinmux program
 that created the [[180nm_Oct2020/pinouts]] and the SVG
 image. The image was used by Greatek for packaging as well as
@@ -84,7 +84,7 @@ JTAG connectivity using jtagremote can then be used on:
 * [[HDL_workflow/ECP5_FPGA]]
 * the actual ls180 ASIC
 
-[[!img 180nm_Oct2020/ls180.svg size="400x" ]]
+<img src="https://ftp.libre-soc.org/course_18oct2021/drawing-4.svg" width=500 />
 
 # Building
 
@@ -111,3 +111,11 @@ These included:
 
 Overall it was a significant amount of work and it is entirely
 automated `RTL2GDS`, no manual intervention required.
+
+<img src="https://ftp.libre-soc.org/course_18oct2021/drawing-2.svg" width=500 />
+
+coriolis2 converts verilog to BLIF using yosys and the Cell Library, then converts
+BLIF into a VHDL subset.  This subset is extremely simple, comprising
+links (netlists) to cells and nothing more. It can be extracted and
+converted to actual VHDL and substituted successfully into verilator,
+ghdl or icarus simulations using cocotb (caveat: the files are enormous).