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[libreriscv.git] / 3d_gpu / requirements_specification.mdwn

diff --git a/3d_gpu/requirements_specification.mdwn b/3d_gpu/requirements_specification.mdwn
index d62657c98ab53feb8f40565d7f76724c1f55cd2a..2956ce5dd587248ca8f3e5d63ed6a2506975b2f7 100644 (file)
--- a/3d_gpu/requirements_specification.mdwn
+++ b/3d_gpu/requirements_specification.mdwn
@@ -248,3 +248,8 @@ So, the multiplier should be capable of 64-bit fmadd, 2x32-bit fmadd,
 (8/16/32/64) sizes of integer mul/mulhsu/mulh/mulhu in 2 groups of 32-bits.
 We can implement fmul using fmadd with 0 (make sure that we get the right
 sign bit for 0 for all rounding modes).
+
+# Rowhammer Mitigation
+
+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000699.html>
+* <https://arxiv.org/pdf/1903.00446.pdf>