Install nmigen (and yosys) by following [[HDL_workflow]]
then follow the excellent tutorial by Robert
<https://github.com/RobertBaruch/nmigen-tutorial> and also look up the
-resources here <https://nmigen.info/nmigen/latest/tutorial.html>
+resources here <https://m-labs.hk/gateware/nmigen/>
Pay particular attention to the bits in HDL workflow about using yosys
"show" command. This is essential because the nmigen code gets turned
blocks in registers (with sync) *before* passing those partial results
back into more (or the same) combinatorial blocks.
-* http://www.clifford.at/yosys/cmd_proc.html
+* https://github.com/YosysHQ/yosys
# verilog