link to raven SoC

[libreriscv.git] / 3d_gpu.mdwn

diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
index 41f1331c962f79447e31527ff7840f03f8b16c86..37a0757aa2a0fd7ad0d0273a8493276e6f9366ff 100644 (file)
--- a/3d_gpu.mdwn
+++ b/3d_gpu.mdwn
@@ -24,6 +24,7 @@ See:
 
 Progress:
 
+* Apr 2019: NLnet funding approved by independent review committee
 * Mar 2019: NLnet funding application first and second phase passed
 * Mar 2019: First successful nmigen pipeline milestone achieved with IEEE754 FADD
 * Feb 2019: Conversion of John Dawson's IEEE754 FPU to nmigen started
@@ -64,4 +65,20 @@ Progress:
 * <https://chips4makers.io/blog/>
 * <https://hackaday.io/project/7817-zynqberry>
 * <https://wiki.f-si.org/index.php/FSiC2019>
-* <https://github.com/efabless/raven-picorv32>
+* <https://github.com/efabless/raven-picorv32> - <https://efabless.com>
+* <https://efabless.com/design_catalog/default>
+* <https://toyota-ai.ventures/>
+* <https://github.com/lambdaconcept/minerva>
+* <https://en.wikipedia.org/wiki/Liskov_substitution_principle>
+* <https://en.wikipedia.org/wiki/Principle_of_least_astonishment>
+* <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
+* <https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md>
+* <https://mshahrad.github.io/openpiton-asplos16.html>
+* <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
+
+# Analog Simulation
+
+* <https://github.com/Isotel/mixedsim>
+* <http://www.vlsiacademy.org/open-source-cad-tools.html>
+* <http://ngspice.sourceforge.net/adms.html>
+* <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>