Add test

[yosys.git] / CHANGELOG

diff --git a/CHANGELOG b/CHANGELOG
index 6f476a2cb82c2a1fa3dc8966fcb933ff750a837f..15dd5d002dfb1002223e7f0ea1f89ca7fd20242a 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -23,7 +23,15 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "muxcover -nopartial"
     - Added "muxpack" pass
     - Added "pmux2shiftx -norange"
-    - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
+    - Added "synth_xilinx -nocarry"
+    - Added "synth_xilinx -nowidelut"
+    - Added "synth_ecp5 -nowidelut"
+    - Added "write_xaiger" backend
+    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
+    - Added "synth_xilinx -abc9" (experimental)
+    - Added "synth_ice40 -abc9" (experimental)
+    - Added "synth -abc9" (experimental)
+    - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
     - Fixed sign extension of unsized constants with 'bx and 'bz MSB