Add test

[yosys.git] / CHANGELOG

diff --git a/CHANGELOG b/CHANGELOG
index c280f4f123a72d3c351f910274243b7ec11cfced..15dd5d002dfb1002223e7f0ea1f89ca7fd20242a 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -23,6 +23,9 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "muxcover -nopartial"
     - Added "muxpack" pass
     - Added "pmux2shiftx -norange"
+    - Added "synth_xilinx -nocarry"
+    - Added "synth_xilinx -nowidelut"
+    - Added "synth_ecp5 -nowidelut"
     - Added "write_xaiger" backend
     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
     - Added "synth_xilinx -abc9" (experimental)