Merge branch 'tux3-implicit_named_connection'

[yosys.git] / CHANGELOG

diff --git a/CHANGELOG b/CHANGELOG
index 5d3b9a5cbd3efd6ff8faedf55ef10971d9c4d24c..36b64e111e9ac8bc09b03ceb3de9d9aff6ee1eeb 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -16,9 +16,9 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "gate2lut.v" techmap rule
     - Added "rename -src"
     - Added "equiv_opt" pass
+    - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
 
 
->>>>>>> upstream/master
 Yosys 0.7 .. Yosys 0.8
 ----------------------