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Add rewrite_sigspecs2, Improve remove() wires
[yosys.git]
/
CHANGELOG
diff --git
a/CHANGELOG
b/CHANGELOG
index 95bbb3f33d44a2ec86fa19cf165a7a4115dae669..36b64e111e9ac8bc09b03ceb3de9d9aff6ee1eeb 100644
(file)
--- a/
CHANGELOG
+++ b/
CHANGELOG
@@
-16,7
+16,7
@@
Yosys 0.8 .. Yosys 0.8-dev
- Added "gate2lut.v" techmap rule
- Added "rename -src"
- Added "equiv_opt" pass
- -
Added "shregmap -tech xilinx", used by "synth_
xilinx"
+ -
"synth_xilinx" to now infer hard shift registers, using new "shregmap -tech
xilinx"
Yosys 0.7 .. Yosys 0.8