kernel: Module::makeblackbox() to clear connections + delete wires last

[yosys.git] / CHANGELOG

diff --git a/CHANGELOG b/CHANGELOG
index 4abfeec06a11a01059d32e8dd3b8be407c9d180a..3b36c3182391c89175338f40aec5c9c5e9636f10 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -8,7 +8,7 @@ Yosys 0.9 .. Yosys 0.9-dev
 
  * Various
     - Added "write_xaiger" backend
-    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
+    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
     - Added "synth_xilinx -abc9" (experimental)
     - Added "synth_ice40 -abc9" (experimental)
     - Added "synth -abc9" (experimental)
@@ -53,13 +53,19 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Added support for flip-flops with synchronous reset to synth_xilinx
     - Added support for flip-flops with reset and enable to synth_xilinx
     - Added "check -mapped"
-    - Added checking of SystemVerilog always block types (always_comb, 
+    - Added checking of SystemVerilog always block types (always_comb,
       always_latch and always_ff)
+    - Added support for SystemVerilog wildcard port connections (.*)
     - Added "xilinx_dffopt" pass
     - Added "scratchpad" pass
-    - Added "abc9 -dff"
     - Added "synth_xilinx -dff"
-    - Improved support of $readmem[hb] file inclusion which is now relative to the Verilog file
+    - Improved support of $readmem[hb] Memory Content File inclusion
+    - Added "opt_lut_ins" pass
+    - Added "logger" pass
+    - Removed "dffsr2dff" (use opt_rmdff instead)
+    - Added "design -delete"
+    - Added "select -unset"
+    - Use YosysHQ/abc instead of upstream berkeley-abc/abc
 
 Yosys 0.8 .. Yosys 0.9
 ----------------------