abc9_ops: fix bypass boxes using (* abc9_bypass *)

[yosys.git] / CHANGELOG

diff --git a/CHANGELOG b/CHANGELOG
index df8e14b26f64666218aa92fc55c56afcaf8cd796..3b36c3182391c89175338f40aec5c9c5e9636f10 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -8,7 +8,7 @@ Yosys 0.9 .. Yosys 0.9-dev
 
  * Various
     - Added "write_xaiger" backend
-    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
+    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
     - Added "synth_xilinx -abc9" (experimental)
     - Added "synth_ice40 -abc9" (experimental)
     - Added "synth -abc9" (experimental)
@@ -58,7 +58,6 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Added support for SystemVerilog wildcard port connections (.*)
     - Added "xilinx_dffopt" pass
     - Added "scratchpad" pass
-    - Added "abc9 -dff"
     - Added "synth_xilinx -dff"
     - Improved support of $readmem[hb] Memory Content File inclusion
     - Added "opt_lut_ins" pass
@@ -66,6 +65,7 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Removed "dffsr2dff" (use opt_rmdff instead)
     - Added "design -delete"
     - Added "select -unset"
+    - Use YosysHQ/abc instead of upstream berkeley-abc/abc
 
 Yosys 0.8 .. Yosys 0.9
 ----------------------