* Various
- Added $changed support to read_verilog
- Added "write_edif -attrprop"
+ - Added "ice40_unlut" pass
+ - Added "opt_lut" pass
+ - Added "synth_ice40 -relut"
+ - Added "synth_ice40 -noabc"
+ - Added "gate2lut.v" techmap rule
+ - Added "rename -src"
+ - Added "equiv_opt" pass
+>>>>>>> upstream/master
Yosys 0.7 .. Yosys 0.8
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