- Added "gate2lut.v" techmap rule
- Added "rename -src"
- Added "equiv_opt" pass
- - Added "shregmap -tech xilinx", used by "synth_xilinx"
+ - Added "read_aiger" frontend
+ - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
Yosys 0.7 .. Yosys 0.8