* Various
- Added $changed support to read_verilog
- Added "write_edif -attrprop"
+ - Added "ice40_unlut" pass
+ - Added "opt_lut" pass
+ - Added "synth_ice40 -relut"
+ - Added "synth_ice40 -noabc"
+ - Added "gate2lut.v" techmap rule
+ - Added "rename -src"
+ - Added "equiv_opt" pass
+ - Added "read_aiger" frontend
+ - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
Yosys 0.7 .. Yosys 0.8