Merge pull request #1086 from udif/pr_elab_sys_tasks2

[yosys.git] / CHANGELOG

diff --git a/CHANGELOG b/CHANGELOG
index 36b64e111e9ac8bc09b03ceb3de9d9aff6ee1eeb..839fefcf1d0b57888408eb5dc20bc8dae561733f 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -16,6 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "gate2lut.v" techmap rule
     - Added "rename -src"
     - Added "equiv_opt" pass
+    - Added "read_aiger" frontend
     - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"