Merge pull request #1086 from udif/pr_elab_sys_tasks2

[yosys.git] / CHANGELOG

diff --git a/CHANGELOG b/CHANGELOG
index a00c2adf85d1829436087820c733fca91ef7697e..839fefcf1d0b57888408eb5dc20bc8dae561733f 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -9,6 +9,15 @@ Yosys 0.8 .. Yosys 0.8-dev
  * Various
     - Added $changed support to read_verilog
     - Added "write_edif -attrprop"
+    - Added "ice40_unlut" pass
+    - Added "opt_lut" pass
+    - Added "synth_ice40 -relut"
+    - Added "synth_ice40 -noabc"
+    - Added "gate2lut.v" techmap rule
+    - Added "rename -src"
+    - Added "equiv_opt" pass
+    - Added "read_aiger" frontend
+    - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
 
 
 Yosys 0.7 .. Yosys 0.8