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ice40_opt to ignore (* keep *) -ed cells
[yosys.git]
/
CHANGELOG
diff --git
a/CHANGELOG
b/CHANGELOG
index 1fc139d498d58d2a7431b2040ae86f8a0583cf05..a49c27b05c76df46a02cc7a44e94c66ea077030a 100644
(file)
--- a/
CHANGELOG
+++ b/
CHANGELOG
@@
-51,6
+51,8
@@
Yosys 0.9 .. Yosys 0.9-dev
- "synth_ice40 -dsp" to infer DSP blocks
- Added latch support to synth_xilinx
- Added "check -mapped"
+ - Added checking of SystemVerilog always block types (always_comb,
+ always_latch and always_ff)
Yosys 0.8 .. Yosys 0.9
----------------------