Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q

[yosys.git] / CHANGELOG

diff --git a/CHANGELOG b/CHANGELOG
index 0adf1e813fa27c36f5c1f9129abf3825106687c3..a49c27b05c76df46a02cc7a44e94c66ea077030a 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -43,6 +43,16 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Added "-match-init" option to "dff2dffs" pass
     - Added "techmap_autopurge" support to techmap
     - Added "add -mod <modname[s]>"
+    - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
+    - Added "ice40_dsp" for Lattice iCE40 DSP packing
+    - Added "xilinx_dsp" for Xilinx DSP packing
+    - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
+    - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
+    - "synth_ice40 -dsp" to infer DSP blocks
+    - Added latch support to synth_xilinx
+    - Added "check -mapped"
+    - Added checking of SystemVerilog always block types (always_comb,
+      always_latch and always_ff)
 
 Yosys 0.8 .. Yosys 0.9
 ----------------------