Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q

[yosys.git] / CHANGELOG

diff --git a/CHANGELOG b/CHANGELOG
index c1ffaa44a18030ad9630a65c2904531d6644d50f..a49c27b05c76df46a02cc7a44e94c66ea077030a 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -50,6 +50,9 @@ Yosys 0.9 .. Yosys 0.9-dev
     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
     - "synth_ice40 -dsp" to infer DSP blocks
     - Added latch support to synth_xilinx
+    - Added "check -mapped"
+    - Added checking of SystemVerilog always block types (always_comb,
+      always_latch and always_ff)
 
 Yosys 0.8 .. Yosys 0.9
 ----------------------