Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q

[yosys.git] / CHANGELOG

diff --git a/CHANGELOG b/CHANGELOG
index f7774cb9e281eb7654db8e8ee47df2786b45e3ee..a49c27b05c76df46a02cc7a44e94c66ea077030a 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -27,6 +27,7 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Improve attribute and parameter encoding in JSON to avoid ambiguities between
       bit vectors and strings containing [01xz]*
     - Added "clkbufmap" pass
+    - Added "extractinv" pass and "invertible_pin" attribute
     - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
     - Added "synth_xilinx -ise" (experimental)
     - Added "synth_xilinx -iopad"
@@ -36,6 +37,22 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
     - Removed "ice40_unlut"
     - Improvements in pmgen: slices, choices, define, generate
+    - Added "xilinx_srl" for Xilinx shift register extraction
+    - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
+    - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
+    - Added "-match-init" option to "dff2dffs" pass
+    - Added "techmap_autopurge" support to techmap
+    - Added "add -mod <modname[s]>"
+    - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
+    - Added "ice40_dsp" for Lattice iCE40 DSP packing
+    - Added "xilinx_dsp" for Xilinx DSP packing
+    - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
+    - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
+    - "synth_ice40 -dsp" to infer DSP blocks
+    - Added latch support to synth_xilinx
+    - Added "check -mapped"
+    - Added checking of SystemVerilog always block types (always_comb,
+      always_latch and always_ff)
 
 Yosys 0.8 .. Yosys 0.9
 ----------------------