Update CHANGELOG

[yosys.git] / CHANGELOG

diff --git a/CHANGELOG b/CHANGELOG
index 5499c309afb83c41ac744bbb4ec29b5c3b320324..c1b548aebbcb4c416733b71fc922987876acfe55 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -3,6 +3,25 @@ List of major changes and improvements between releases
 =======================================================
 
 
+Yosys 0.8 .. Yosys 0.8-dev
+--------------------------
+
+ * Various
+    - Added $changed support to read_verilog
+    - Added "write_edif -attrprop"
+    - Added "ice40_unlut" pass
+    - Added "opt_lut" pass
+    - Added "synth_ice40 -relut"
+    - Added "synth_ice40 -noabc"
+    - Added "gate2lut.v" techmap rule
+    - Added "rename -src"
+    - Added "equiv_opt" pass
+    - Added "read_aiger" frontend
+    - Added "muxpack" pass
+    - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
+    - "synth_xilinx" to now infer wide multiplexers
+
+
 Yosys 0.7 .. Yosys 0.8
 ----------------------