Update example for GW1NR-9

[yosys.git] / CHANGELOG

diff --git a/CHANGELOG b/CHANGELOG
index afbcffa26dd6e2f80f429b8727e1be164da09624..c2942929561c7700cb92ab5c52bdc6ada51ea625 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -3,9 +3,45 @@ List of major changes and improvements between releases
 =======================================================
 
 
-Yosys 0.8 .. Yosys 0.9
+Yosys 0.9 .. Yosys 0.9-dev
 --------------------------
 
+ * Various
+    - Added "write_xaiger" backend
+    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
+    - Added "synth_xilinx -abc9" (experimental)
+    - Added "synth_ice40 -abc9" (experimental)
+    - Added "synth -abc9" (experimental)
+    - Added "script -scriptwire"
+    - Added "synth_xilinx -nocarry"
+    - Added "synth_xilinx -nowidelut"
+    - Added "synth_ecp5 -nowidelut"
+    - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
+    - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
+    - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
+    - Renamed labels in synth_intel (e.g. bram -> map_bram)
+    - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
+    - Added automatic gzip decompression for frontends
+    - Added $_NMUX_ cell type
+    - Added automatic gzip compression (based on filename extension) for backends
+    - Improve attribute and parameter encoding in JSON to avoid ambiguities between
+      bit vectors and strings containing [01xz]*
+    - Added "clkbufmap" pass
+    - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
+    - Added "synth_xilinx -ise" (experimental)
+    - Added "synth_xilinx -iopad"
+    - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
+    - Improvements in pmgen: subpattern and recursive matches
+    - Added "opt_share" pass, run as part of "opt -full"
+    - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
+    - Removed "ice40_unlut"
+    - Improvements in pmgen: slices, choices, define, generate
+    - Added "xilinx_srl" for Xilinx shift register extraction
+    - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
+
+Yosys 0.8 .. Yosys 0.9
+----------------------
+
  * Various
     - Many bugfixes and small improvements
     - Added support for SystemVerilog interfaces and modports
@@ -111,7 +147,7 @@ Yosys 0.8 .. Yosys 0.9
     - Added support for initialising BRAM primitives from a file
     - Added iCE40 Ultra RGB LED driver cells
 
- * Xilinx support 
+ * Xilinx support
     - Use "write_edif -pvector bra" for Xilinx EDIF files
     - Fixes for VPR place and route support with "synth_xilinx"
     - Added more cell simulation models