- Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
- Removed "ice40_unlut"
- Improvements in pmgen: slices, choices, define, generate
+ - Added "xilinx_srl" for Xilinx shift register extraction
+ - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
Yosys 0.8 .. Yosys 0.9
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