tests: opt_expr update xnor/xor tests

[yosys.git] / CHANGELOG

diff --git a/CHANGELOG b/CHANGELOG
index a49c27b05c76df46a02cc7a44e94c66ea077030a..df8e14b26f64666218aa92fc55c56afcaf8cd796 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -50,9 +50,22 @@ Yosys 0.9 .. Yosys 0.9-dev
     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
     - "synth_ice40 -dsp" to infer DSP blocks
     - Added latch support to synth_xilinx
+    - Added support for flip-flops with synchronous reset to synth_xilinx
+    - Added support for flip-flops with reset and enable to synth_xilinx
     - Added "check -mapped"
     - Added checking of SystemVerilog always block types (always_comb,
       always_latch and always_ff)
+    - Added support for SystemVerilog wildcard port connections (.*)
+    - Added "xilinx_dffopt" pass
+    - Added "scratchpad" pass
+    - Added "abc9 -dff"
+    - Added "synth_xilinx -dff"
+    - Improved support of $readmem[hb] Memory Content File inclusion
+    - Added "opt_lut_ins" pass
+    - Added "logger" pass
+    - Removed "dffsr2dff" (use opt_rmdff instead)
+    - Added "design -delete"
+    - Added "select -unset"
 
 Yosys 0.8 .. Yosys 0.9
 ----------------------