- "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
- "synth_ice40 -dsp" to infer DSP blocks
- Added latch support to synth_xilinx
+ - Added support for flip-flops with synchronous reset to synth_xilinx
+ - Added support for flip-flops with reset and enable to synth_xilinx
- Added "check -mapped"
- Added checking of SystemVerilog always block types (always_comb,
always_latch and always_ff)
- - Added "clkpart" pass
+ - Added support for SystemVerilog wildcard port connections (.*)
+ - Added "xilinx_dffopt" pass
+ - Added "scratchpad" pass
+ - Added "abc9 -dff"
+ - Added "synth_xilinx -dff"
+ - Improved support of $readmem[hb] Memory Content File inclusion
+ - Added "opt_lut_ins" pass
+ - Added "logger" pass
+ - Removed "dffsr2dff" (use opt_rmdff instead)
+ - Added "design -delete"
+ - Added "select -unset"
Yosys 0.8 .. Yosys 0.9
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