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[libreriscv.git] / Cesar_Strauss.mdwn

diff --git a/Cesar_Strauss.mdwn b/Cesar_Strauss.mdwn
index f700443b3a320a1450102b0260b8e25a9fdcf4c0..492a8f24a5ffbb29b66abec333fab07b823b200b 100644 (file)
--- a/Cesar_Strauss.mdwn
+++ b/Cesar_Strauss.mdwn
@@ -62,11 +62,18 @@ unit tests.
         <https://bugs.libre-soc.org/show_bug.cgi?id=565>  
         Status: in progress  
 
+13. Implement simple VL for-loop in nMigen for TestIssuer  
+        <https://bugs.libre-soc.org/show_bug.cgi?id=583>  
+        Status: in progress  
+
 ## Completed but not yet submitted:
 
 1. FSM-based ALU example needed (compliant with ALU CompUnit)  
        <https://bugs.libre-soc.org/show_bug.cgi?id=417>  
-       
+
+2. Fix MSB0 issues in the SVP64 Assembler, Simulator and Decoder  
+       <https://bugs.libre-soc.org/show_bug.cgi?id=600>
+
 ## Submitted for NLNet RFP
 
 ## Paid