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[libreriscv.git] / Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn

diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
index 03498bc82611de803c2ea43cbca7ceff5ac1427e..a6d7f78cef61f8cd5e039d60060d3b50017fc106 100644 (file)
--- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
+++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
@@ -1,5 +1,51 @@
 # Comparative analysis with Andes Packed ISA proposal
 
+## Register file
+
+| Register           | Andes ISA                    | Harmonised RVP ISA        |
+| ------------------ | -------------------------    | -------------------       |
+| v0                 | Hardwired zero               | Hardwired zero            |
+| v1                 | 32bit GPR or Vector[4xB|2xH] | Predicate masks           |
+| v2                 | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xSB] |
+| v3                 | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xSB] |
+| v4                 | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xSB] |
+| v5                 | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xSB] |
+| v6                 | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xSB] |
+| v7                 | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xSB] |
+| v8                 | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xUB] |
+| v9                 | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xUB] |
+| v10                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xUB] |
+| v11                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xUB] |
+| v12                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xUB] |
+| v13                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xUB] |
+| v14                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xUB] |
+| v15                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[4xUB] |
+| v16                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xSH] |
+| v17                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xSH] |
+| v18                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xSH] |
+| v19                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xSH] |
+| v20                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xSH] |
+| v21                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xSH] |
+| v22                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xSH] |
+| v23                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xSH] |
+| v24                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xUH] |
+| v25                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xUH] |
+| v26                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xUH] |
+| v27                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xUH] |
+| v28                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xUH] |
+| v29                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[2xUH] |
+| v30                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[1xUW] |
+| v31                | 32bit GPR or Vector[4xB|2xH] | 32bit GPR or Vector[1xUW] |
+
+
+
+| RADD16 rt, ra, rb  | Signed Halving add        | RADD (r16 <= rt,ra,rb <= r23), mm=00|
+| URADD16 rt, ra, rb | Unsigned Halving add      | RADD (r24 <= rt,ra,rb <= r29), mm=00|
+| KADD16 rt, ra, rb  | Signed Saturating add     | VADD (r16 <= rt,ra,rb <= r23), mm=01|
+| UKADD16 rt, ra, rb | Unsigned Saturating add   | VADD (r24 <= rt,ra,rb <= r29), mm=01|
+| SUB16 rt, ra, rb   | Subtract                  | VSUB (r16 <= rt,ra,rb <= r29), mm=00|
+| RSUB16 rt, ra, rb  | Signed Halving sub        | RSUB (r16 <= rt,ra,rb <= r23), mm=00|
+
 ## 16-bit Arithmetic
 
 | Andes Mnemonic           | 16-bit Instruction        | Harmonised RVP Equivalent |
@@ -105,10 +151,28 @@ Andes SIMD Packed ISA omits 8 bit shifts, but these can be encoded in Harmonised
 
 ## 16-bit Miscellaneous instructions
 
-| Andes Mnemonic           | 16-bit Instruction        | Harmonised RVP Equivalent |
+| Andes Mnemonic      | 16-bit Instruction                | Harmonised RVP Equivalent |
+| ------------------  | ------------------------          | ------------------- |
+| SMIN16 rt, ra, rb   | Signed minimum                    | VMIN (r16 <= rt,ra,rb <= r23), mm=00|
+| UMIN16 rt, ra, rb   | Unsigned minimum                  | VMIN (r24 <= rt,ra,rb <= r29), mm=00|
+| SMAX16 rt, ra, rb   | Signed maximum                    | VMAX (r16 <= rt,ra,rb <= r23), mm=00|
+| UMAX16 rt, ra, rb   | Unsigned maximum                  | VMAX (r24 <= rt,ra,rb <= r29), mm=00|
+| SCLIP16 rt, ra, rb  | Signed clip                       | ?VCLIP (r16 <= rt,ra,rb <= r23), mm=01|
+| UCLIP16 rt, ra, rb  | Unsigned clip                     | ?VCLIP (r24 <= rt,ra,rb <= r29), mm=01|
+| KMUL16 rt, ra, rb   | Signed multiply 16x16->16         | VMUL (r16 <= rt,ra,rb <= r23), mm=01|
+| KMULX16 rt, ra, rb  | Signed crossed multiply 16x16->16 | |
+| SMUL16 rt, ra, rb   | Signed multiply 16x16->32         | VMUL (30 <= rt <= 31, r16 <= ra,rb <= r23), mm=00|
+| SMULX16 rt, ra, rb  | Signed crossed multiply 16x16->32 | |
+| UMUL16 rt, ra, rb   | Signed multiply 16x16->32         | VMUL (30 <= rt <= 31, r24 <= ra,rb <= r31), mm=00|
+| UMULX16 rt, ra, rb  | Signed crossed multiply 16x16->32 | |
+| KABS16 rt, ra, rb   | Saturated absolute value          | VSGNX (r16 <= rt <= r29, r16 <= ra,rb <= r23, mm=01) |
+
+## 8-bit Miscellaneous instructions
+
+| Andes Mnemonic           | 8-bit Instruction        | Harmonised RVP Equivalent |
 | ------------------   | ------------------------- | ------------------- |
-| SMIN16 rt, ra, rb   | Signed minimum           | VMIN (r16 <= rt,ra,rb <= r23), mm=00|
-| UMIN16 rt, ra, rb   | Unsigned minimum         | VMIN (r24 <= rt,ra,rb <= r29), mm=00|
-| SMAX16 rt, ra, rb   | Signed maximum           | VMAX (r16 <= rt,ra,rb <= r23), mm=00|
-| UMAX16 rt, ra, rb   | Unsigned maximum         | VMAX (r24 <= rt,ra,rb <= r29), mm=00|
-| KABS16 rt, ra, rb   | Saturated absolute value | VSGNX (r16 <= rt <= r29, 16 <= ra,rb <= 23, mm=01 |
+| SMIN8 rt, ra, rb   | Signed minimum           | VMIN (r2 <= rt,ra,rb <= r7), mm=00|
+| UMIN8 rt, ra, rb   | Unsigned minimum         | VMIN (r8 <= rt,ra,rb <= r15), mm=00|
+| SMAX8 rt, ra, rb   | Signed maximum           | VMAX (r2 <= rt,ra,rb <= r7), mm=00|
+| UMAX8 rt, ra, rb   | Unsigned maximum         | VMAX (r8 <= rt,ra,rb <= r15), mm=00|
+| KABS8 rt, ra, rb   | Saturated absolute value | VSGNX (r2 <= rt <= r15, r2 <= ra,rb <= r8, mm=01) |