(no commit message)

[libreriscv.git] / Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn

diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
index a3671bb82c05b611ee96763cf4ffd49b2643b48d..ca8055d81a8a102d09c14e9ef3ccf24c16a0fc71 100644 (file)
--- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
+++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
@@ -1,4 +1,8 @@
-# Comparative analysis of Andes Packed ISA proposal vs RVP Harmonised (with RV Vector spec)
+# Comparative analysis of Andes Packed ISA proposal vs Harmonised RVP
+
+Harmonised RVP is a proposal to provide SIMD functionality comparable to the Andes Packed SIMD ISA, but in a manner that is forwards compatible ("harmonised") with the RV Vector specification.
+
+An example use case is a string copy operation - using Harmonised RVP, binary code using integer register based SIMD to copy a string of bytes can also execute (unchanged) on a full RV Vector processor and use the dedicated vector unit to copy string.  The is also upwards compatibility between RV32 and RV64 SIMD using this same approach.
 
 ## Register file comparison